CNTFET-based design of dynamic ternary full adder cell

Murotiya, Sneh Lata; Gupta, Anu; Vasishth, Sparsh

doi:10.1109/indicon.2014.7030403

Cited by 5 publications

(5 citation statements)

References 17 publications

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“…The new designs and the previous dynamic TFA [17] are simulated in three different power supply voltages (1, 0.9, and 0.8 V) at 400 MHz clock frequency and room temperature. Fan‐out of four ternary inverters (FO4) is used as the output load for each output (Sum and C out ) to provide a realistic and standard setup [25].…”

Section: Simulation Resultsmentioning

confidence: 99%

“…Though the proposed TFA has one more transistor than the one presented in [16], the static TFA is not capable of adding three ‘ 2 ’s. Similar to the previous dynamic TFA [17], it is also based on the assumption that the third input variable, c , never becomes ‘ 2 ’. The new structure is in conformity with the classic and typical definition of a full adder cell.…”

Section: Simulation Resultsmentioning

confidence: 99%

“…Several high‐performance static ternary adders have been proposed in the literature [13–16]. A dynamic ternary full adder (TFA) has been also presented in [17] recently. Despite its attempt at transistor reduction, it has major drawbacks.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

From static ternary adders to high‐performance race‐free dynamic ones

Rezaie

Mirzaee

Navi

et al. 2015

J. eng.

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Section: Simulation Resultsmentioning

confidence: 99%

Section: Simulation Resultsmentioning

confidence: 99%

See 1 more Smart Citation

From static ternary adders to high‐performance race‐free dynamic ones

Rezaie

Mirzaee

Navi

et al. 2015

J. eng.

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“…We have found 125 related papers [11–135], 20% of which have been published in IEEE journals. To be more specific, there are 15 IEEE Transactions [11–25], five IEEE Access [26–30], and two JSSC papers [31, 32].…”

Section: Literature Review and Backgroundmentioning

confidence: 99%

“…Nonetheless, a dynamic circuit requires an additional CLK signal and confronts cascading and charge sharing problems. 90.4% of the previous designs are based on static logic, and only a few are based on dynamic logic [49, 50, 61, 62, 83, 85, 88–90]. It is worth mentioning that the functionality of quantum‐dot cellular automata designs is also based on the four clock signals incorporated in this technology [82, 91].…”

Section: Literature Review and Backgroundmentioning

confidence: 99%

Comprehensive survey of ternary full adders: Statistics, corrections, and assessments

Nemati

Kashani

Mirzaee

2023

IET Circuits, Devices & Syst

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The history of ternary adders goes back to more than 6 decades ago. Since then, a multitude of ternary full adders (TFAs) have been presented in the literature. This article conducts a review of TFAs so that one can be familiar with the utilised design methodologies and their prevalence. Moreover, despite numerous TFAs, almost none of them are in their simplest form. A large number of transistors could have been eliminated by considering a partial TFA instead of a complete one. According to our investigation, only 28.6% of the previous designs are partial TFAs. Also, they could have been simplified even further by assuming a partial TFA with an output carry voltage of 0 V or V DD . This way, in a single-V DD design, voltage division inside the Carry generator part would have been eliminated and less power dissipated. As far as we have searched, there are only three partial TFAs with this favourable condition in the literature. Additionally, most of the simulation setups in the previous articles are not realistic enough. Therefore, the simulation results reported in these papers are neither comparable nor entirely valid. Therefore, the authors got motivated to conduct a survey, elaborate on this issue, and enhance some of the previous designs. Among 84 papers, 10 different TFAs (from 11 papers) are selected, simplified, and simulated in this article. Simulation results by HSPICE and 32 nm carbon nanotube FET technology reveal that the simplified partial TFAs outperform their original versions in terms of delay, power, and transistor count. K E Y W O R D Sadders, carbon nanotube field effect transistors, digital arithmetic, multivalued logic, multivalued logic circuits, ternary logicThis is an open access article under the terms of the Creative Commons Attribution-NonCommercial License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited and is not used for commercial purposes.

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A review on the design of ternary logic circuits*

Wang

Dong

2021

Chinese Phys. B

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A multi-valued logic system is a promising alternative to traditional binary logic because it can reduce the complexity, power consumption, and area of circuit implementation. This article briefly summarizes the development of ternary logic and its advantages in digital logic circuits. The schemes, characteristics, and application of ternary logic circuits based on CMOS, CNTFET, memristor, and other devices and processes are reviewed in this paper, providing some reference for the further research and development of ternary logic circuits.

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CNTFET-based design of dynamic ternary full adder cell

Cited by 5 publications

References 17 publications

From static ternary adders to high‐performance race‐free dynamic ones

From static ternary adders to high‐performance race‐free dynamic ones

Comprehensive survey of ternary full adders: Statistics, corrections, and assessments

A review on the design of ternary logic circuits*

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