CMP-PIM: An Energy-Efficient Comparator-based Processing-In-Memory Neural Network Accelerator

Angizi, Shaahin; He, Zhezhi; Rakin, Adnan Siraj; Fan, Deliang

doi:10.1109/dac.2018.8465860

Cited by 30 publications

(32 citation statements)

References 10 publications

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“…The possible reasons that there was a lack of concerns on the security of network parameters may come in twofold: 1) The neural network is widely recognized as a robust system against parameter variations. 2) The DNNs are used to be only deployed on the high-performance computing system (e.g., CPUs, GPUs, and other accelerators [13,14]), which normally contains a variety of methods ensuring data integrity. Thus, attacking the parameters is more related to a system cyber-security topic.…”

Section: Introductionmentioning

confidence: 99%

Bit-Flip Attack: Crushing Neural Network With Progressive Bit Search

Rakin

Fan

2019

2019 IEEE/CVF International Conference on Computer Vision (ICCV)

Self Cite

135

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Several important security issues of Deep Neural Network (DNN) have been raised recently associated with different applications and components. The most widely investigated security concern of DNN is from its malicious input, a.k.a adversarial example. Nevertheless, the security challenge of DNN's parameters is not well explored yet. In this work, we are the first to propose a novel DNN weight attack methodology called Bit-Flip Attack (BFA) which can crush a neural network through maliciously flipping extremely small amount of bits within its weight storage memory system (i.e., DRAM). The bit-flip operations could be conducted through well-known Row-Hammer attack, while our main contribution is to develop an algorithm to identify the most vulnerable bits of DNN weight parameters (stored in memory as binary bits), that could maximize the accuracy degradation with a minimum number of bit-flips. Our proposed BFA utilizes a Progressive Bit Search (PBS) method which combines gradient ranking and progressive search to identify the most vulnerable bit to be flipped. With the aid of PBS, we can successfully attack a ResNet-18 fully malfunction (i.e., top-1 accuracy degrade from 69.8% to 0.1%) only through 13 bit-flips out of 93 million bits, while randomly flipping 100 bits merely degrades the accuracy by less than 1%.

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Section: Introductionmentioning

confidence: 99%

Bit-Flip Attack: Crushing Neural Network With Progressive Bit Search

Rakin

Fan

2019

2019 IEEE/CVF International Conference on Computer Vision (ICCV)

Self Cite

135

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“…When some local features are not well extracted, the local denoising effect will be degraded. Recently, depthwise separable convolution (DSConv) has been used in many advanced neural networks, such as Xception [ 42 ], MobileNets [ 43 ], and MobileNets2 [ 44 ], to replace the standard convolutional layer, aiming to reduce CNN computational cost and to extract local features [ 45 ].…”

Section: Methodsmentioning

confidence: 99%

Denoising of 3D Brain MR Images with Parallel Residual Learning of Convolutional Neural Network Using Global and Local Feature Extraction

Liu

2021

Computational Intelligence and Neuroscience

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Magnetic resonance (MR) images often suffer from random noise pollution during image acquisition and transmission, which impairs disease diagnosis by doctors or automated systems. In recent years, many noise removal algorithms with impressive performances have been proposed. In this work, inspired by the idea of deep learning, we propose a denoising method named 3D-Parallel-RicianNet, which will combine global and local information to remove noise in MR images. Specifically, we introduce a powerful dilated convolution residual (DCR) module to expand the receptive field of the network and to avoid the loss of global features. Then, to extract more local information and reduce the computational complexity, we design the depthwise separable convolution residual (DSCR) module to learn the channel and position information in the image, which not only reduces parameters dramatically but also improves the local denoising performance. In addition, a parallel network is constructed by fusing the features extracted from each DCR module and DSCR module to improve the efficiency and reduce the complexity for training a denoising model. Finally, a reconstruction (REC) module aims to construct the clean image through the obtained noise deviation and the given noisy image. Due to the lack of ground-truth images in the real MR dataset, the performance of the proposed model was tested qualitatively and quantitatively on one simulated T1-weighted MR image dataset and then expanded to four real datasets. The experimental results show that the proposed 3D-Parallel-RicianNet network achieves performance superior to that of several state-of-the-art methods in terms of the peak signal-to-noise ratio, structural similarity index, and entropy metric. In particular, our method demonstrates powerful abilities in both noise suppression and structure preservation.

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“…However, the majority of the inputs/outputs are moved across MAC arrays and from global buffers. Table 2 [49][50][51][52][53][54][55][56][57][58][59][60][61] reviews parts of recently emerged embedded NVM-based MAC operations. Most of the publications were applied to inference applications and depend on ADC-DAC blocks for signal conversion.…”

Section: Architecture-level Explorationmentioning

confidence: 99%

“…Numerous in-MRAM computing schemes have been demonstrated using on-chip arrays to realize fundamental Boolean logic operations (i.e., AND, OR, XOR, and FA) and complex arithmetical functions (i.e., neural networks). Table 3 [26,31,34,58,59,[68][69][70][71][72][73][74][75][76] shows the literature study on recent in-MRAM computing. Main approaches are executed using bit-cell modification, reference adaptation, PTL-enabled NMC, and in-memory analog computation schemes.…”

Section: The State-of-the-art Of In-mram Computingmentioning

confidence: 99%

A survey of in-spin transfer torque MRAM computing

Cai

Liu

Chen

et al. 2021

Sci. China Inf. Sci.

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In traditional von Neumann computing architectures, the essential transfer of data between the processor and memory hierarchies limits the computational efficiency of next-generation system-on-a-chip. The emerging in-memory computing (IMC) approach addresses this issue and facilitates the movement of significant data and rapid computations. Among the different memory types, intrinsic energy efficiency is demonstrated by in-magnetic random access memory (MRAM) computing with a low-power spintronic magnetic tunnel junction device and hybrid integration at an advanced complementary metal-oxide semiconductor node. This study reviews state-of-the-art techniques for managing IMC with an emphasis on spin-transfer torque-MRAM computing via design schemes at the bit-cell, circuit, and system levels. In addition, this study presents effective design techniques and potential challenges and demonstrates the existing limitations of in-MRAM computing and potential methods for overcoming these issues. This study also considers the design technology co-optimization from the IMC perspective.

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CMP-PIM: An Energy-Efficient Comparator-based Processing-In-Memory Neural Network Accelerator

Cited by 30 publications

References 10 publications

Bit-Flip Attack: Crushing Neural Network With Progressive Bit Search

Bit-Flip Attack: Crushing Neural Network With Progressive Bit Search

Denoising of 3D Brain MR Images with Parallel Residual Learning of Convolutional Neural Network Using Global and Local Feature Extraction

A survey of in-spin transfer torque MRAM computing

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