CMOS transistor sizing for minimization of energy-delay product

Tretz, C.; Zukowski, C.

doi:10.1109/glsv.1996.497614

Cited by 11 publications

(8 citation statements)

References 3 publications

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“…For small geometries the effects of parasitic wiring capacitance must be considered in the PDP models. 32 In this research, the following expressions 32 were used for the optimal device sizing…”

Section: Pdp Productmentioning

confidence: 99%

Implementation of Low Power Digital Multipliers Using 10 Transistor Adder Blocks

Kudithipudi¹,

John²

2005

Journal of Low Power Electronics

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The increasing demand for the high fidelity portable devices has laid emphasis on the development of low power and high performance systems. In the next generation processors, the low power design has to be incorporated into fundamental computation units, such as multipliers. The characterization and optimization of such low power multipliers will aid in comparison and choice of multiplier modules in system design. In this paper we performed a comparative analysis of the power, delay, and power delay product (PDP) optimization characteristics of four parallel digital multipliers implemented using low power 10 transistor (10T) adders and conventional CMOS adder cells. In order to achieve optimal power savings at smaller geometry sizes, we proposed a heuristic approach known as hybrid adder models. Multipliers realized using the Static Energy Recovery Full adder (SERF) circuit consumed considerably less power compared to 10T and static CMOS based multipliers for all the configurations studied. Furthermore, the difference between the power consumption of the 10 transistor based multipliers and 28T multipliers is significant at 180 nm, but not at 70 nm. For smaller geometry sizes down to 70 nm, the propagation delay of the multipliers implemented with 10 transistors translates to a better performance measure. Carry-Save Multipliers had better PDP range than the other multipliers for all the three adder sub-module designs. The PDP measure for optimal scaled gate width resulted in a best-case scenario for SERF Wallace tree multiplier as compared to the other three SERF based multipliers. This can be attributed to the fast computational capability of the Wallace Tree multiplier and SERF adders' recovery energy logic saving more power at deep sub-micron sizes. The proposed SERF-10T Hybrid adder model multipliers consumed the least power of all the Hybrid and regular models with no deterioration in performance. Taken together, these results suggest that SERF-10T Hybrid model based multipliers are suited for ultra low power design and fast computation at smaller geometry sizes.

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Section: Pdp Productmentioning

confidence: 99%

Implementation of Low Power Digital Multipliers Using 10 Transistor Adder Blocks

Kudithipudi¹,

John²

2005

Journal of Low Power Electronics

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“…They present elegant solutions to optimize repeaters with and without area constraints; however, the repeater is modeled as a simple linear resistor and capacitor and no closed form solution is provided. Other repeater insertion methods are described in [8]- [10]. In [11] and [12], buffer placement methodologies in multisink topologies based on minimizing the Elmore delay are presented.…”

Section: Introductionmentioning

confidence: 99%

“…Consequently, the scaled CRT become a very useful technique in many RNS-implemented DSP-algorithms, that often require operations, such as sign detection, division, and overflow handling. Different scaled CRT-implementations have been presented in the literature [4]- [8], [10], [11]. The precision of the scaled output depends on the application and ranges from low, in the case of approximate sign detection [6], to very high precision, for exact sign detection and scaled conversion [7], [10], [11].…”

Section: Introductionmentioning

confidence: 99%

“…In [5], [7], and [10], a scaling factor of the form P = 2 d =M has been used. In [8] and [11], a more general scaling factor has been used. In particular, in [8], P 2 [1; M ], but in order to avoid the "catastrophic error band", a reduced dynamic range must be used.…”

Section: Introductionmentioning

confidence: 99%

“…In [8] and [11], a more general scaling factor has been used. In particular, in [8], P 2 [1; M ], but in order to avoid the "catastrophic error band", a reduced dynamic range must be used. In the scaling factor, P must be such that P > N , being N the number of moduli used in the RNS representation.…”

Section: Introductionmentioning

confidence: 99%

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Uniform repeater insertion in RC trees

Adler¹,

Friedman²

2000

IEEE Trans. Circuits Syst. I

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Repeater insertion can be used to overcome the quadratic increase in the time required for a signal to propagate through an interconnect. A new timing model, based on short-channel equations, has been developed to characterize the signal delay through a resistive line. These analytical expressions provide the foundation for algorithms used to insert uniform repeaters into tree structures. Both local and global optimization algorithms for repeater insertion are presented. While the local optimization algorithm provides a computationally fast solution to the repeater insertion problem, the resulting circuit implementation is less power, area, and speed efficient than applying global optimization techniques. The global optimization algorithm for repeater insertion is achieved through the downhill simplex method. The circuit equations, algorithms, and software implementation of this repeater insertion system are presented in this paper.Results from these insertion methodologies improve delay from 25% to 60% versus typical cascaded buffer methodologies. Global repeater insertion further decreases delay times by up to 22% over the local repeater insertion method. The accuracy of the timing model characterizing the repeater insertion process as compared to SPICE simulations is generally within 10%. Applications of these algorithms for minimizing the signal delay through an tree, such as in data paths, and targeting signal delays through an tree, such as in clock distribution networks, are also discussed.

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Trade-Offs in CMOS VLSI Circuits

Mezhiba

Friedman

Trade-Offs in Analog Circuit Design

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CMOS transistor sizing for minimization of energy-delay product

Cited by 11 publications

References 3 publications

Implementation of Low Power Digital Multipliers Using 10 Transistor Adder Blocks

Implementation of Low Power Digital Multipliers Using 10 Transistor Adder Blocks

Uniform repeater insertion in RC trees

Trade-Offs in CMOS VLSI Circuits

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