CMOS ternary dynamic differential logic

Herrfeld, A.; Hentschke, S.

doi:10.1049/el:19940542

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Cited by 12 publications

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“…The description of 3-valued memory elements is found in the references [10], [11]. In present work, it is suggested that flip-flops based on new ternary clocked gates reduces number of T-gates as compared with the clocked T-gates proposed in [3], [12], [13]. Fig.1 (a) & implementation of STI, NTI &PTI is given in Fig.1 (b).…”

Section: Introductionmentioning

confidence: 94%

DESIGN OF 3-VALUED R-S & D FLIP-FLOPS BASED ON SIMPLE TERNARY GATES

Dhande¹,

Ingole²

2005

Int. J. Soft. Eng. Knowl. Eng.

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Design of 3-valued R-S & D type of flip-flops is described. A new clock is developed according to which circuit makes transition as well as retains present, past & former past information. The proposed flip-flops are constructed using clocked T-Gates that reduces the number of transistors required to implement single clocked gates. In the verification by simulation, the proposed flip-flops appears to have lesser power consumption and better speed of operation.

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Section: Introductionmentioning

confidence: 94%