CMOS reliability issues for emerging cryogenic Lunar electronics applications

Abstract

We investigate the reliability issues associated with the application of CMOS devices contained within an advanced SiGe HBT BiC-MOS technology to emerging cryogenic space electronics (e.g., down to 43 K, for Lunar missions). Reduced temperature operation improves CMOS device performance (e.g., transconductance, carrier mobility, subthreshold swing, and output current drive), as expected. However, operation at cryogenic temperatures also causes serious device reliability concerns, since it aggravates hot-carrier effects, effectively decreasing the inferred device lifetime significantly, especially at short gate lengths. In the paper, hot-carrier effects are demonstrated to be a stronger function of the device gate length than the temperature, suggesting that significant trade-offs between the gate length and the operational temperature must be made in order to ensure safe and reliable operation over typical projected mission lifetimes in these hostile environments.

Performance and Low-Frequency Noise of 22-nm FDSOI Down to 4.2 K for Cryogenic Applications

“…8. The lines indicate the carrier number fluctuations with correlated mobility fluctuations (CNF/CMF) analytical model described in equation (1), where Ω is a noise parameter related to the Coulomb scattering coefficient and S Vfb is the flat band voltage power spectral density related to the trapping/detrapping of carriers in slow oxide states [23]. Since good agreement between the data and the model is obtained from 300K down to 4.2K, we can conclude that carrier number fluctuation and correlated mobility fluctuation are the sources of noise, and the 1/f noise to signal power increases with T lowering because of the g m /I DS improvement, on the same way as previously found for bulk CMOS [24].…”

“…HE interest in cryogenic electronics relies on several applications, such as space and cooling systems [1], [2], and has been recently boosted by the quantum computing field [3], [4]. Recently, monolithic integration between qubits and readout circuitry has been demonstrated at 2K in 22nm FDSOI technology [5], and the electrical performance of several CMOS technologies has shown to be significantly improved with temperature (T) decrease [6]- [8].…”

Signal Processing for Particle Detectors

“…Recently emerging cryogenic applications have generated renewed interest in low temperature properties of both CMOS and HBT technologies [54,55]. As with HBTs, it has been found that various CMOS device properties improve at low temperatures.…”

Degradations of Threshold Voltage, Mobility, and Drain Current and the Dependence on Transistor Geometry For Stressing at 77 K and 300 K

“…Fig. 1 shows the degradation curves with stress time for 2 µm/0.13 µm transistors at room temperature (RT) and for the stress voltage of 2.6 V. Up to 10% of the drain current degradation and the threshold voltage degradation, both curves follow the classical power law format ‫ݕ‬ = ‫ݐܣ‬ [5]- [9][9] [11] (where A is a free fitting parameter that depends on stress voltage, t is stress time and n is a parameter containing information on the degradation mechanisms and may depend on the technology.) However, at around 2000 seconds when the mobility degradation is 13%, the curve shows a departure from the classical law.…”