Cmos Memory Circuits

Haraszti, T.P.

doi:10.1007/b117067

Cited by 13 publications

(5 citation statements)

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“…On the other hand, the speed of the complementary operation (for the given example, the reading of a logic '1' in the bit-line) will have the opposite behavior. This is in accordance to (10), as it is expected that imbalances in the sense amplifier may act against the logic '0' or the logic '1'.…”

Section: Resultssupporting

confidence: 86%

“…Therefore, despite its dynamic memory core, its interface is simple, similar to static memories. Its performance, though, is slightly slower than its static counterpart (10). These memories consist of a number of circuits, such as: the memory cell array, row decoders, column decoders, sense amplifiers and the self-refresh.…”

Section: Introductionmentioning

confidence: 99%

“…The reason for this choice is the fact that TID effects can cause a reduction in the operation margin of sense amplifiers. For differential voltage sense amplifiers, especially, operation margin may degrade due to imbalances caused by non-uniform parameter variations throughout the circuit (10). Moreover, the increased leakage current through the access transistor of a 1T-DRAM cell could lead to a significant charge reduction in the storage capacitor.…”

Section: Introductionmentioning

confidence: 99%

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Analysis of Total Ionizing Dose Effects on a Pseudo-Static Random Access Memory (PSRAM)

et al. 2012

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The purpose of this work is to describe the total ionizing dose effects on a commercial ISSI 4Mb pseudo-static random access memory (PSRAM). Experimental results from an irradiation test performed at the Ionizing Radiation Laboratory at Instituto de Estudos Avançados (LRI/IEAv) using a Co-60 gamma-radiation source were analyzed and compared to simulation results of typical memory circuits and typical memory architecture, in order to identify error patterns and failure mechanisms.

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Section: Resultssupporting

confidence: 86%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Analysis of Total Ionizing Dose Effects on a Pseudo-Static Random Access Memory (PSRAM)

et al. 2012

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“…for modern computers. 1,2) Recently, it is also studied as a candidate for weight memories in deep neural network (DNN) inference accelerators. [3][4][5] The 6TSRAM which does not require the refresh operation to retain its data is one of the most user-friendly semiconductor memories.…”

Section: Introductionmentioning

confidence: 99%

A gate leakage current-powered loadless 4T SRAM with immunity against random dopant fluctuation and surface roughness in silicon-silicon dioxide interface

Zhu

Ohsawa

2022

Jpn. J. Appl. Phys.

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The sensitivities of the data hold, read and write performances for the gate leakage-powered loadless 4T SRAM cell on the variations in the MOSFETs’ gate leakage currents are examined by SPICE Monte Carlo simulations in 32nm technology. The standard deviations in the gate leakage current variations are taken from the device simulation results in which the variations are caused by the random dopant fluctuation and the surface roughness in silicon-silicon dioxide interface. It is shown that the static noise margin (SNM) in the data hold state is 60mV at 1V power supply voltage for the -5 sigma cell with the MOSFETs’ threshold voltage variations taken into consideration. The read SNM and the write SNM are shown to be 160mV and 440mV for the -5 sigma cell, respectively, which are better than the 6T SRAM cell.

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“…In recent years, embedded Flash memories are widely used in SOCs (System On chip) targeting the mobile communications, micro-controllers, smart cards and contact-less cards for on-chip nonvolatile storage with high operation speeds as well as low power consumption [1,2,3]. Read speed is mainly determined by the read path, which is affected in a non-negligible way by the sense amplifier's speed performance, and becomes critical when the power supply is reduced [4].…”

Section: Introductionmentioning

confidence: 99%

A Sense Amplifier for Low Voltage Embedded Flash Memories

Zhang

2014

AMR

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A sense amplifier applied for low voltage embedded flash memories is presented. The sense amplifier uses an enhanced current sensing method allowing power supplies lower than 1.5 V to be used. The sense amplifier was implemented in a FLASH realized with a 0.13 um FLASH technology. Simulation results showed a read access time of about 25 ns with a power supply of 1.5 V, and 32ns with a power supply of 1.2V.

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Cmos Memory Circuits

Cited by 13 publications

References 0 publications

Analysis of Total Ionizing Dose Effects on a Pseudo-Static Random Access Memory (PSRAM)

Analysis of Total Ionizing Dose Effects on a Pseudo-Static Random Access Memory (PSRAM)

A gate leakage current-powered loadless 4T SRAM with immunity against random dopant fluctuation and surface roughness in silicon-silicon dioxide interface

A Sense Amplifier for Low Voltage Embedded Flash Memories

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