A gate leakage current-powered loadless 4T SRAM with immunity against random dopant fluctuation and surface roughness in silicon-silicon dioxide interface

Abstract

The sensitivities of the data hold, read and write performances for the gate leakage-powered loadless 4T SRAM cell on the variations in the MOSFETs’ gate leakage currents are examined by SPICE Monte Carlo simulations in 32nm technology. The standard deviations in the gate leakage current variations are taken from the device simulation results in which the variations are caused by the random dopant fluctuation and the surface roughness in silicon-silicon dioxide interface. It is shown that the static noise margin (SNM) in the data hold state is 60mV at 1V power supply voltage for the -5 sigma cell with the MOSFETs’ threshold voltage variations taken into consideration. The read SNM and the write SNM are shown to be 160mV and 440mV for the -5 sigma cell, respectively, which are better than the 6T SRAM cell.

Area-efficient Binarized Neural Network Inference Accelerator Based on Time-multiplexed XNOR Multiplier Using Loadless 4T SRAM

“…Since this ensures the consistency of the weight optimization by the training software with the weight values stored in the 6TSRAM cells, higher inference accuracies are expected in the high-density accelerator Fig. 2 shows the loadless 4T SRAM cell whose data are sustained by the access PFETs' subthreshold leakage currents [15][16][17] or their gate leakage currents [18][19][20][21]. The cell size is reduced by 17% compared with the 6TSRAM cell (see Fig.…”

“…Fig. 3 shows the comparison of the write trigger voltages between the 6TSRAM cell and the loadless 4T SRAM cell (It is shown that the write margin of the loadless 4T SRAM is larger than the 6TSRAM [19].). It is shown that the write trigger voltage of the loadless 4T SRAM cell is much higher than that of the 6TSRAM cell.…”

“…Fig. 2 The loadless 4T SRAM cell powered by the gate tunneling leakage current with BL disturb free [18][19][20][21].…”

“…5 (a) shows the simulated loadless 4T SRAM nodes' voltages during reading operation for the input +1 which is based on the conventional XNOR logic. Though the gate leakage of Q1 provides enough current to sustain the data in the loadless 4T SRAM cell during the holding period [18][19][20][21], this current is much smaller than the current flowing through Q2 to GND due to a high voltage in the gate of Q2 by the current flow from BL to the node B. So, the synapse suffers from the read disturb under the conventional XNOR reading mode, showing that the XNOR multiplier and the accumulator scheme in Fig.…”

“…In this paper, we propose a current sensing scheme for an XNOR multiplier based on the loadless 4T SRAM cell [15][16][17][18][19][20][21] which is applied to the MAC operation in binarized neural network (BNN) inference accelerators. The current sense amplifiers for SRAM were proposed about 30 years ago [22][23][24].…”