CMOS leaf-cell design using simulated annealing

Abstract

l%is paper describes a program which uses simulated annealing to optimize two-dimensional, full-custom, symbolic CMOS leaf-cell layouts given a circuit4evel netlist. User input specifies groups of series andpamllel transistor connections with up to three levels of logic hierarchy. Simulated annealing is used for selecting group placemen&. A new cost function is presented for the simulated annealing algorithm which is based on channel congestion as well as estimated interconnect cost.The general problem of automating layout design of CMOS leaf-cells has received considerable attention in the technical literature. Work in this area can be roughly classified as two types, one-dimensional layout [ 11-[3] and two-dimensional layout [4]- [6]. Although all these algorithms seek to minimize cell area, the algorithms are based on either maximizing transistor abutments or channel density, or minimizing the total wiring length.CMOS Leaf-cell Automatic Designer (CLAD) applies simulated annealing [7] to minimize the layout area of two-dimensional, full-custom symbolic CMOS leaf-cell layouts given a circuitlevel netlist [ 151. This CLAD netlist can be manually written or automatically generated from HDL behavioral descriptions using BLACK [14], [16]. The CLAD netlist specifies groups of series and parallel transistor connections with up to three levels of logic hierarchy. Simulated annealing determines placement of grouped transistors which may contain NMOS topology, PMOS topology, transmission gates or any combination of these three. Unlike applications of simulated annealing for placement of standard cells which contain hundreds or even thousands of placement members, CLAD employs simulated annealing for placements of tens or hundreds of groups. Placement, routing, and 1ayouE are generated in two or three minutes such as is required for interactive design. S i -PiaPlacement of leaf-cell groups specified in the CLAD netlist starts from a randomly-generated arrangement. From this arrangement, two groups are selected for exchange using the C built-in uniform, pseudo-random number generator. Placements are evaluated by a cost function which approximates the total cell area.As the simulated annealing proceeds, the process temperature decreases. Early in the annealing, when the process temperature 1516 0-7803-0510-8/92$03.W Q1992IEEEis still high, more unfavorable exchanges are accepted to allow escape from local minima. As the annealing process continues, with the temperature decreasing according to a cooling schedule, fewer and fewer unfavorable exchanges are accepted.Favorable exchanges where Acost is negative are always accepted, as are neutral exchanges where Acost is zero. Exchanges with increased cost are characterized by a metricp which is a function of Acost and process temperature Z p = e. ( - +)An unfavorable exchange is accepted if the metricp is greater than a randomly generated number on the interval (0.1). Early in the annealing, when the temperature Tis high, the metricp is generally large, and thus it is more lik...

Simulated annealing: Practice versus theory

“…Applications to more complex circuit design problems including several layers of logic hierarchy were approached using SQ [32]. This required placements and routing for tens to hundreds of groups of units, potentially a higher dimensional task than placing individual connections among units.…”

Efficient Adaptive Monte Carlo Uncertainty Forecasting for High Dimensional Nonlinear Dynamic Systems

“…As described in [28], SA offers an alternative approach to the original architecture of the ensemble enhancer within AMC. SA has been utilized to study the traveling salesman problem, in circuit design, the design of decision trees, in data analysis, imaging and neural networks, as well as in areas of biology, physics, finance, and the military, among others [52], [53], [54], [55], [56], [57], [58], [59], [60], [61]. As SA is inherently sequential, significant research has been conducted to not only increase its serial efficiency, but also to parallelize the algorithm while maintaining convergence properties or, at the very least, induce minimal errors in the algorithm.…”