2014
DOI: 10.1109/jssc.2014.2313561
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CMOS Doherty Amplifier With Variable Balun Transformer and Adaptive Bias Control for Wireless LAN Application

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Cited by 32 publications
(13 citation statements)
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“…However, a quarter wave TLine is hard to implement in CMOS as the losses would simply be too high (Reynaert, Cao et al, 2016). Several papers (Ryu, Jang et al, 2014;Reynaert, Cao et al, 2016;Kim, Lee & Hong, 2016) report using series combining transformers in order to imitate the loadpull effect. The effect is reduced, comparing to the traditional DPA, but the benefit of combining a Class AB and a Class C PA still results in a higher overall efficiency and a possibly increased bandwidth.…”
Section: Doherty Architecturementioning
confidence: 99%
See 1 more Smart Citation
“…However, a quarter wave TLine is hard to implement in CMOS as the losses would simply be too high (Reynaert, Cao et al, 2016). Several papers (Ryu, Jang et al, 2014;Reynaert, Cao et al, 2016;Kim, Lee & Hong, 2016) report using series combining transformers in order to imitate the loadpull effect. The effect is reduced, comparing to the traditional DPA, but the benefit of combining a Class AB and a Class C PA still results in a higher overall efficiency and a possibly increased bandwidth.…”
Section: Doherty Architecturementioning
confidence: 99%
“…Both designed DPAs are summarized and compared to the target specifications in Table 3.7. (Cui, Roblin et al, 2007) 0.18 μm CMOS 3.7 3.5 24.4 36.1 6 (Ryu, Jung & Jeong, 2012) (Kim, Son et al, 2014) 0.18 μm CMOS -0.89 25 43.6 5 (Ryu, Jang et al, 2014) 0 The designed DPA parameters are summarized and compared to those presented in the similar CMOS process scale in Table 3.8. Both designed DPA configurations are on par with the published DPAs, but is designed to operate at a much higher 6.5 GHz frequency with a smaller supply voltage.…”
Section: Classical and Simplified Doherty Power Amplifier Configuratimentioning
confidence: 99%
“…A DPA using a variable balun transformer as impedance inverter is analyzed in [61]: it achieves load modulation without any phase delay circuit, thus reducing the total chip area. Additionally, adaptive bias control of the auxiliary stage assists the load modulation, resulting in an improved back-off efficiency.…”
Section: A Silicon Technologymentioning
confidence: 99%
“…Among different efficiency enhancement techniques such as envelope-tracking [19], [20] and Doherty [7], [21]- [31], Doherty PA [21] is still one of the most widely used efficiency enhancement techniques, because of its relatively simple and low-cost implementation. Using an off-chip matching network reduces the passives losses, thus increasing the efficiency especially at PBO compared to implementations with on-chip matching network [27]- [29].…”
Section: Introductionmentioning
confidence: 99%