CMOS device optimization for system-on-a-chip applications

Imai, K.; Yamaguchi, Koji; Kudo, Teruo; Kimizuka, N.; Onishi, H.; Ono, Akira; Nakahara, Y.; Noda, K.; Masuoka, S.; Ito, Shotaro; Matsui, K.; Ando, Koji; Hasegawa, Eiji; Ohashi, T.; Oda, Noriaki; Yokoyama, K.; Takewaki, T.; Sone, S.; Horiuchi, T.

doi:10.1109/iedm.2000.904354

Cited by 10 publications

(6 citation statements)

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“…The CMOS technology optimized for the best digital performance may not give good analog performance for mixed-signal applications [5]. Hence, with the logic device technology poised for the 90 nm technology generation, it has become essential to look for alternative solutions to meet the analog performance requirements for mixed mode applications.…”

mentioning

confidence: 99%

Impact of lateral asymmetric channel doping on deep submicrometer mixed-signal device and circuit performance

Narasimhulu

Sharma

Rao

2003

IEEE Trans. Electron Devices

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mentioning

confidence: 99%

Impact of lateral asymmetric channel doping on deep submicrometer mixed-signal device and circuit performance

Narasimhulu

Sharma

Rao

2003

IEEE Trans. Electron Devices

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“…The gate leakage current of NMOS is 4 to 10 times greater than that of P-type metal oxide semiconductor (PMOS) of the same thickness. Figure 2 shows the relation between the measured gate tunneling current of the MOS transistor and gate voltage in our 45 nm CMOS logic technology (Imai et al, 2000). The equivalent gate-oxide thickness is 2.0 nm.…”

Section: Gate Leakage Issuementioning

confidence: 99%

“…I gp-i (I gp-i) and I gp-a are the gate leakage currents of unit width in the inversion mode and the accumulation mode, respectively. The standby leakage current of a memory cell can be estimated by the sum of I g-cell and I off-cell, here, gateinduced drain leakage (GIDL) is ignored because it is smaller than 1/10 of the total drain leakage current in our 45 nm CMOS technology (Imai et al, 2000). Since the inversion current of NMOS is dominant in gate leakage currents (Figure 2), the third term in (1) is the most dominant factor.…”

Section: Memory Cellmentioning

confidence: 99%

Design and analysis of 45 nm low power 32 kb embedded static random access memory (SRAM) cell

Akashe¹

2012

Int. J. Phys. Sci.

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In sub-100 nm generation, gate-tunneling leakage current increases and dominates the total standby leakage current of LSIs based on decreasing gate-oxide thickness. Showing that the gate leakage current is effectively reduced by lowering the gate voltage, we propose a local DC level control (LDLC) for static random access memory (SRAM) cell arrays and an automatic gate leakage suppression driver (AGLSD) for peripheral circuits. We designed and analyzed a 32 kb 1-port SRAM using 45 nm CMOS technology. The six-transistor SRAM cell size is 1.25 µm 2. Evaluation shows that the standby current of 32 kb SRAM is 1.2 µA at 1.2 V and room temperature. It was reduced to 7.5% of the conventional SRAM.

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“…In addition, these methods may not be effective when the cache utilization is high (unused cache parts reduced significantly). Gate leakage reduction by depositing thin gate oxide only to critical path using dual or triple gate oxide technology [7] is practically unfeasible due to the difficulty in controlling the gate oxide locally.…”

Section: Introductionmentioning

confidence: 99%

DG-SRAM: A Low Leakage Memory Circuit

Elakkumanan

Thondapu

Sridhar

2005 Joint 30th International Conference on Infrared and Millimeter Waves and 13th International Conference on Terahertz Electr

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The gate oxide thickness in sub-70mm process technologies approaches the limit where direct gate tunneling current starts to play a significant role in both off-state and on-state transistors. This gate leakage current coupled with the subthreshold leakage, results in a dramatic increase in total leakage power. Hence, efficient power reduction strategies that directly address the gate leakage component are necessary. In this paper, we present a novel Diode-Gated SRAM (DG-SRAM) that uses two additional NMOS (or PMOS) transistors to decrease the gate leakage in Very Deep Sub-Micron (VDSM) cache and embedded memories. Our simulation results on 65nm process (Berkeley Predictive Technology Model) for an oxide thickness of 1.5nm indicate a reduction of about 69% of the gate leakage and 65% of total leakage for NMOS-connected DG-SRAM as compared to the conventional SRAM, with minimal area overhead and no significant loss in performance or stability.

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CMOS device optimization for system-on-a-chip applications

Cited by 10 publications

References 0 publications

Impact of lateral asymmetric channel doping on deep submicrometer mixed-signal device and circuit performance

Impact of lateral asymmetric channel doping on deep submicrometer mixed-signal device and circuit performance

Design and analysis of 45 nm low power 32 kb embedded static random access memory (SRAM) cell

DG-SRAM: A Low Leakage Memory Circuit

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