CMOS Continuous-Time Adaptive Equalizers for High-Speed Serial Links

Aldea, C.; Gasca, Cecilia Gimeno; Pueyo, Santiago Celma

doi:10.1007/978-3-319-10563-5

Cited by 2 publications

(4 citation statements)

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“…8 In Table 1 the characteristics of the proposed circuit are summarized and compared with the published paper in Refs. [7][8][9]. As shown in the table, higher data rate is achieved in the Ref.…”

Section: Experiments Resultsmentioning

confidence: 81%

“…The Ref. [9] consumes less power because of single stage equalizer amplifier and no limiting amplifier adopted in their architecture, resulting in lower gain in the low frequency. Compared with the Ref.…”

Section: Experiments Resultsmentioning

confidence: 99%

“…[7] Ref. [9] Ref. [8] This work Process (μm) 0.13 0.18 0.13 0.13 Data rate (Gb/s) 0.28 (2) 0.36 (3) 0.23 (4) Supply voltage (V) 1.…”

Section: Parametermentioning

confidence: 99%

“…Once the eye diagram is too narrow or totally closed, the data cannot be detected correctly by the next device. A straightforward solution for re-shaping the eye is to design an adaptive equalizer [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16] in the receiver with automatic tuning capability; by this method it would not result in an under-or over-compensation for the attenuation of high-frequency components. Linear analog equalizer [1,[7][8][9][10][11][12] , which can provide good ISI and jitter cancellation with acceptable power dissipation and integration complexity, has been developed widely in multi-Gb/s applications.…”

Section: Introductionmentioning

confidence: 99%

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A 5 Gb/s CMOS adaptive equalizer for serial link

Wang

Liu

2018

J. Semicond.

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A 5 Gb/s adaptive equalizer with a new adaptation scheme is presented here by using 0.13 μm CMOS process. The circuit consists of the combination of equalizer amplifier, limiter amplifier and adaptation loop. The adaptive algorithm exploits both the low frequency gain loop and the equalizer loop to minimize the inter-symbol interference (ISI) for a variety of cable characteristics. In addition, an offset cancellation loop is used to alleviate the offset influence of the signal path. The adaptive equalizer core occupies an area of 0.3567 mm 2 and consumes a power consumption of 81.7 mW with 1.8 V power supply. Experiment results demonstrate that the equalizer could compensate for a designed cable loss with 0.23 UI peak-to-peak jitter.

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Section: Experiments Resultsmentioning

confidence: 81%

Section: Experiments Resultsmentioning

confidence: 99%

“…[7] Ref. [9] Ref. [8] This work Process (μm) 0.13 0.18 0.13 0.13 Data rate (Gb/s) 0.28 (2) 0.36 (3) 0.23 (4) Supply voltage (V) 1.…”

Section: Parametermentioning

confidence: 99%