A 5 Gb/s CMOS adaptive equalizer for serial link

Abstract

A 5 Gb/s adaptive equalizer with a new adaptation scheme is presented here by using 0.13 μm CMOS process. The circuit consists of the combination of equalizer amplifier, limiter amplifier and adaptation loop. The adaptive algorithm exploits both the low frequency gain loop and the equalizer loop to minimize the inter-symbol interference (ISI) for a variety of cable characteristics. In addition, an offset cancellation loop is used to alleviate the offset influence of the signal path. The adaptive equalizer core occupies an area of 0.3567 mm 2 and consumes a power consumption of 81.7 mW with 1.8 V power supply. Experiment results demonstrate that the equalizer could compensate for a designed cable loss with 0.23 UI peak-to-peak jitter.

A 36 Gb/s wireline receiver with adaptive CTLE and 1-tap speculative DFE in 0.13 µm BiCMOS technology

“…Ref. [20] introduced that there are two loops in the adaptive continuous time equalizer for detecting high frequency and low frequency components, respectively. However, there is interference between the two loops.…”