Clustering and linear placement

Schuler, Donald M.; Ulrich, Ernst G.

doi:10.1145/800153.804929

Cited by 98 publications

(29 citation statements)

References 6 publications

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“…Finally, we use a clustering algorithm [22] to group small macros into large ones based on the size constraint, and the criticality and connectivity between macros. Let be the connected graph where is the set of macro nodes and the set of edges.…”

Section: B Soft-macro Formationmentioning

confidence: 99%

A timing-driven soft-macro placement and resynthesis method in interaction with chip floorplanning

Lin

1999

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-In this paper, we present a complete chip design method which incorporates a soft-macro placement and resynthesis method in interaction with chip floorplanning for area and timing improvements. We present a performance-driven soft-macro clustering and placement method which preserves hardware descriptive language (HDL) design hierarchy to guide the soft-macro placement process. We develop a timing-driven design flow to exploit the interaction between HDL synthesis and physical design tasks. During each design iteration, we resynthesize soft macros with either a relaxed or a tightened timing constraint which is guided by the post-layout timing information. The goal is to produce area-efficient designs while satisfying the timing constraints. Experiments on a number of industrial designs ranging from 75-K to 230-K gates demonstrate that the proposed soft-macro clustering and placement method improves critical-path delays on an average of 22%. Furthermore, the results show that by effectively relaxing the timing constraint of noncritical modules and tightening the timing constraint of critical modules, a design can achieve 11% to 30% timing improvements with little to no increase in chip area.

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Section: B Soft-macro Formationmentioning

confidence: 99%

A timing-driven soft-macro placement and resynthesis method in interaction with chip floorplanning

Lin

1999

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Let us first demonstrate the importance of geographical location for decomposition on a simple example. Consider the case of decomposing a gate with four input pins and respective arrival times t AT,1 … t AT,4 , as shown in Figure 1a. Assume the order of arrival times to be t AT,1 t AT,2 t AT,3 t AT, 4 , however, all arrival times are within close range, i.e.…”

Section: Decompositionmentioning

confidence: 99%

“…Consider the case of decomposing a gate with four input pins and respective arrival times t AT,1 … t AT,4 , as shown in Figure 1a. Assume the order of arrival times to be t AT,1 t AT,2 t AT,3 t AT, 4 , however, all arrival times are within close range, i.e. the slowest signal is only marginally slower than the fastest signal, or identical.…”

Section: Decompositionmentioning

confidence: 99%

“…pin p 1 and p 2 of gate g 1 and group them into a 2-input gate. Following, pins p 3 and p 4 , now the fastest pins will be decomposed. It is obvious that due to the geographical location of the feeding signals, this will not only cause longer net length, but also higher wiring congestion.…”

Section: Decompositionmentioning

confidence: 99%

“…It is obvious that due to the geographical location of the feeding signals, this will not only cause longer net length, but also higher wiring congestion. Consequently, the better choice is to decompose pins p 1 and p 4 and their respective nets n 1 and n 4 into gate g 2 , and nets n 2 and n 3 feeding pins p 2 and p 3 into gate g 3 , as shown in Figure 1b, effectively resulting in shorter wiring length and better congestion. In conclusion, we comprehend that it is important to group input pins into a gate to be extracted those signal origins are close to each other.…”

Section: Decompositionmentioning

confidence: 99%

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Congestion aware layout driven logic synthesis

Kutzschebauch¹,

Stok²

IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281)

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In this paper, we present novel algorithms that effectively combine physical layout and early logic synthesis to improve overall design quality. In addition, we employ partitioning and clustering algorithms to achieve faster turn around times.With the increasing complexity of designs, the traditional separation of logic and physical design leads to sub-optimal results as the cost functions employed during logic synthesis do not accurately represent physical design information. While this problem has been addressed extensively, the existing solutions apply only simple synthesis transforms during physical layout and are generally unable to reverse decisions made during logic minimization and technology mapping, that have a major negative impact on circuit structure.In our novel approach, we propose congestion aware algorithms for layout driven decomposition and technology mapping, two of the steps that affect congestion the most during logic synthesis, to effectively decrease wire length and improve congestion. In addition, to improve design turn-around-time and handle large designs, we present an approach in which synthesis partitioning and placement clustering co-exist, reflecting the different characteristics of logical and physical domain.

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On metaheuristic algorithms for combinatorial optimization problems

Yagiura

Ibaraki

2001

Syst. Comp. Jpn.

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PrefaceThere are numerous combinatorial optimization problems, for which computing exact optimal solutions is computationally intractable, e.g., those problems known as NP-hard. However, in practice, we are often asked to deal with large scale instances of such difficult problems. One possibility to overcome this difficulty is that, in most practical cases, we do not need exact optimal solutions and are satisfied with sufficiently good solutions. In this sense, approximate (or heuristic) algorithms, which provide reasonably good solutions in practically meaningful time, are very important and have been well studied recently.There are several useful tools used to design approximate algorithms, such as greedy method and local search. The so-called metaheuristics combine these tools into more sophisticated algorithms. Among the well-known metaheuristics are multi-start local search, simulated annealing, tabu search, genetic algorithm and so on. Many variants of these, such as GRASP, threshold accepting, iterated local search and others, have also been proposed and extensively studied.One of the attractive features of these metaheuristics is in its flexibility. They can be hybridized with other heuristic or exact algorithms to create more powerful tools. As an example of such hybrid algorithms, we propose to use dynamic programming (DP) to improve candidate solutions within the framework of genetic algorithm, which is called the genetic DP algorithm. Good prospects of the proposed algorithm are observed by the computational experiments to three representative NP-hard problems: single machine scheduling problem, optimal linear arrangement problem and traveling salesman problem.During the experience of developing the genetic DP, we realized that crossover is one of the most important operators in genetic algorithms, on which the overall performance of the algorithms critically depends. To pursue this direction, we review a variety of crossover operators proposed for sequencing problems, and analyze the relationship between characteristics of the operator and performance of the algorithm. Based on this analysis, we propose simple criteria for measuring the quality of crossover operators. Some computational analysis on single machine scheduling problem is then added to validate the effectiveness of the proposed criteria.Another attractive feature of metaheuristics is in its robustness and simplicity. They i can be developed even if deep mathematical properties of the problem domain are not at hand, and still can provide reasonably good solutions, much better than those obtainable by simple heuristics. To investigate this direction, we compare representative metaheuristic algorithms using rather simple inner operators to observe general tendency of their performance. From these results, we propose a recommendation about the use of metaheuristics as simple optimization tools.We then consider a problem arising from the implementation issue of a crossover operator.

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Clustering and linear placement

Cited by 98 publications

References 6 publications

A timing-driven soft-macro placement and resynthesis method in interaction with chip floorplanning

A timing-driven soft-macro placement and resynthesis method in interaction with chip floorplanning

Congestion aware layout driven logic synthesis

On metaheuristic algorithms for combinatorial optimization problems

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