Closeness metrics for system-level functional partitioning

Vahid, Frank; Gajski, Daniel D.

doi:10.1109/eurdac.1995.527425

Cited by 25 publications

(16 citation statements)

References 15 publications

(3 reference statements)

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“…Works dealing with metrics in the domain of high-level synthesis [17,18] and hardware software co-design [19][20][21] have been recently proposed. In [17] the metrics provide algorithm properties regarding a hardware implementation; the quantified metrics address the concurrency of arithmetic operations based on uniformed scheduling probabilities and the regularity that measures the repetition rate of a given pattern.…”

Section: Review Of Existing Metricsmentioning

confidence: 99%

“…These metrics focus on a fine grain analysis and are mainly used to guide the design of datapaths, especially to optimize local connections and resource reuse. The metrics from [19] are computed at the functional level to highlight resource, data and communication channel sharing capabilities in order to perform a pre-partitioning resulting in function clustering to guide the next design step (hardware/software partitioning). The main issue is the placement of close functions on the same component in order to optimize communications and resource sharing.…”

Section: Review Of Existing Metricsmentioning

confidence: 99%

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Algorithmic-level Specification and Characterization of Embedded Multimedia Applications with Design Trotter

Moullec

Diguet

Amor

et al. 2006

J VLSI Sign Process Syst Sign Image Video Technol

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Designing embedded systems is a challenging task during which wrong choices can lead to extremely costly re-design loops, especially when these wrong choices are made during the algorithm specification and the mapping over the selected architecture. In this paper we propose a high-level approach for design space exploration, using a usual standard language as input. More precisely we present the two first steps of the Design Trotter framework: (i) the specification step and its underlying internal model (HCDFG: Hierarchical and Control Data Flow Graph) and (ii) the characterization step which takes place very early in the design flow. Indeed, once transformed into our internal representation, the specification is rapidly and automatically characterized and explored at the algorithmic level. The framework provides the designer with metrics so that he can evaluate, very early in the design process, the impact of algorithmic choices on resource requirements in terms of processing, control, memory bandwidth and potential parallelism at different levels of granularity. The overall aim of our approach is to improve the algorithm/architecture matching that sorely influences the implementation efficiency in terms of silicon area, performances and energy consumption. We give examples which illustrate how designers can refer to the outcomes of the Design Trotter framework in order to select or build suitable architectures for specific applications.

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Section: Review Of Existing Metricsmentioning

confidence: 99%

Section: Review Of Existing Metricsmentioning

confidence: 99%

Algorithmic-level Specification and Characterization of Embedded Multimedia Applications with Design Trotter

Moullec

Diguet

Amor

et al. 2006

J VLSI Sign Process Syst Sign Image Video Technol

View full text Add to dashboard Cite

show abstract

“…They proposed a partitioner driven by the closeness metrics, which provides the designer with a measure on how efficient a solution could be, one that implements two different components on the same side, HW or SW. This technique was further improved with a procedural partitioning [19,20]. Vahid and Gajski [19] proposed a set of closeness metrics for a functional partitioning at the system level.…”

Section: Reconfigurable Systems and Codesignmentioning

confidence: 99%

“…This technique was further improved with a procedural partitioning [19,20]. Vahid and Gajski [19] proposed a set of closeness metrics for a functional partitioning at the system level.…”

Section: Reconfigurable Systems and Codesignmentioning

confidence: 99%

An ILP Formulation for the Task Graph Scheduling Problem Tailored to Bi-dimensional Reconfigurable Architectures

Redaelli

Santambrogio

Memik

2008

2008 International Conference on Reconfigurable Computing and FPGAs

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This work proposes an exact ILP formulation for the task scheduling problem on a 2D dynamically and partially reconfigurable architecture. Our approach takes physical constraints of the target device that is relevant for reconfiguration into account. Specifically, we consider the limited number of reconfigurators, which are used to reconfigure the device. This work also proposes a reconfiguration-aware heuristic scheduler, which exploits configuration prefetching, module reuse, and antifragmentation techniques. We experimented with a system employing two reconfigurators. This work also extends the ILP formulation for a HW/SW Codesign scenario. A heuristic scheduler for this extension has been developed too. These systems can be easily implemented using standard FPGAs. Our approach is able to improve the schedule quality by 8.76% on average (22.22% in the best case). Furthermore, our heuristic scheduler obtains the optimal schedule length in 60% of the considered cases. Our extended analysis demonstrated that HW/SW codesign can indeed lead to significantly better results. Our experiments show that by using our proposed HW/SW codesign method, the schedule length of applications can be reduced by a factor of 2 in the best case.

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“…Previous works dealing with metrics have been completed in the areas of high-level synthesis [9,6] and hardware software codesign [9,18,19]. In [1] the metrics provide algorithm properties regarding a hardware implementation.…”

Section: Metricsmentioning

confidence: 99%

Design of a multimedia processor based on metrics computation

Amor

Moullec

Diguet³

et al. 2005

Advances in Engineering Software

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Media-processing applications, such as signal processing, 2D and 3D graphics rendering, and image compression, are the dominant workloads in many embedded systems today. The real-time constraints of those media applications have taxing demands on today's processor performances with low cost, low power and reduced design delay. To satisfy those challenges, a fast and efficient strategy consists in upgrading a low cost general purpose processor core. This approach is based on the personalization of a general RISC processor core according the target multimedia application requirements. Thus, if the extra cost is justified, the general purpose processor GPP core can be enforced with instruction level coprocessors, coarse grain dedicated hardware, ad hoc memories or new GPP cores. In this way the final design solution is tailored to the application requirements. The proposed approach is based on three main steps: the first one is the analysis of the targeted application using efficient metrics. The second step is the selection of the appropriate architecture template according to the first step results and recommendations. The third step is the architecture generation. This approach is experimented using various image and video algorithms showing its feasibility.Key words: design space exploration, media processor, graph-based specification, guidance, metrics 1-IntroductionWe are currently experiencing an important increase in the use of embedded devices with powerful multimedia capabilities such as speech analysis and synthesis, character recognition, video compression, and graphics animation. Due to the various needs of such applications, embedded devices have to handle various data types and various complex tasks under hard real-time constraints. The need for real-time processing of complex algorithms is further accentuated by the increasing interest in other new domains like 3D image. Especially in the domain of embedded systems, the main design constraint is the time to market priority since the availability of a new product at short time even not perfectly optimised is the key point for its commercial success. Another important point in this domain is the opportunity to take advantage of the application characteristics in order to optimize the energy / time / QoS tradeoff. Thus, our strategy is to define a framework that provides a simple and fast analysis tool. The first point is to start with a typical software specification which is automatically transformed into a graph-based internal representation. The idea is to take as an input a standard code without performing any additional effort and to analyze it. Even if the false data dependencies have been eliminated, the resulting hierarchical graph still reflects the designer or standard authors point of view. If such a specification fits with a low cost, low power embedded processor, this is probably the more interesting solution. Secondly, our objective is to extract from the various granularity levels of this specification opportunities of paralleli...

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Closeness metrics for system-level functional partitioning

Cited by 25 publications

References 15 publications

Algorithmic-level Specification and Characterization of Embedded Multimedia Applications with Design Trotter

Algorithmic-level Specification and Characterization of Embedded Multimedia Applications with Design Trotter

An ILP Formulation for the Task Graph Scheduling Problem Tailored to Bi-dimensional Reconfigurable Architectures

Design of a multimedia processor based on metrics computation

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