An ILP Formulation for the Task Graph Scheduling Problem Tailored to Bi-dimensional Reconfigurable Architectures

Abstract

This work proposes an exact ILP formulation for the task scheduling problem on a 2D dynamically and partially reconfigurable architecture. Our approach takes physical constraints of the target device that is relevant for reconfiguration into account. Specifically, we consider the limited number of reconfigurators, which are used to reconfigure the device. This work also proposes a reconfiguration-aware heuristic scheduler, which exploits configuration prefetching, module reuse, and antifragmentation techniques. We experimented with a system employing two reconfigurators. This work also extends the ILP formulation for a HW/SW Codesign scenario. A heuristic scheduler for this extension has been developed too. These systems can be easily implemented using standard FPGAs. Our approach is able to improve the schedule quality by 8.76% on average (22.22% in the best case). Furthermore, our heuristic scheduler obtains the optimal schedule length in 60% of the considered cases. Our extended analysis demonstrated that HW/SW codesign can indeed lead to significantly better results. Our experiments show that by using our proposed HW/SW codesign method, the schedule length of applications can be reduced by a factor of 2 in the best case.

A multiobjective reconfiguration-aware scheduler for FPGA-based heterogeneous architectures

“…In literature there are many approaches addressing variants of the RCSP problem that rely on heuristic algorithms ( [2], [5]- [7], [10], [11]) and exact algorithms ( [2]- [4], [8], [12]). What follows is a description of these works in which we highlight their contributions and limitations.…”

“…The reconfiguration time is directly proportional to the bitstream size of the area that has to be reconfigured, the smaller the area the quicker is the reconfiguration. Hence, module reuse [2] (i.e., sharing resources among equal tasks that have already been placed on the FPGA) is desirable in order to reduce the number of reconfigurations. Another important feature is reconfiguration prefetching, which allows the configuration of a task to be performed ahead of time, prior to actually requiring the corresponding task execution, hence the reconfiguration time can be hidden more effectively by the execution of other tasks.…”

“…Such requirements refer not only to the overall execution time (like most of the other schedulers in the literature do [2]- [8]), but also to power and energy consumption of the design. This means addressing a specific Resource Constrained Scheduling Problem (RCSP) [9], that takes into consideration the reconfiguration aspects with a focus on power and energy metrics that are becoming crucial in designing applications targeting heterogeneous architectures.…”

A Replacement Technique to Maximize Task Reuse in Reconfigurable Systems

“…Integer Linear Programming (ILP) formulations [11,12] to schedule DAGs in reconfigurable systems fall into this group. These approaches can reach optimal results; however they are impractical even for small instances, since they do not scale well when increasing the sizes of the target architectures and of the input task graphs.…”

“…Finally, for the end_of_execution event (10), the manager checks again if the reconfiguration circuitry is idle. In that case, it invokes the replacement module (11)(12)(13). After that, it updates the taskgraph dependencies, decreasing by 1 the number of predecessors of each successor of the finished task (14).…”