Closed-Loop Control and Performance Evaluation of Reduced Part Count Multilevel Inverter Interfacing Grid-Connected PV System

Abstract

Multilevel inverters (MLIs) have drawn tremendous attention in the power sector. Application of MLI has grown extensively to improve the power quality and efficiency of the photovoltaic (PV) system. For an MLI interfacing PV system, the size, cost and voltage stress are the key constraints of the MLI that need to be minimized. This paper presents a novel reduced part count MLI interfacing single-stage grid-tied PV system along with a closed-loop control strategy. The proposed MLI consists of n repeating units and a level boosting circuit (LBC) that assists in generating 4n + 7 voltage levels instead of 2n + 3 levels. Three different algorithms are proposed for a proper selection of dc-link voltages to enhance the levels further. A comparative analysis is carried out to confirm the superiority of the developed MLI. The workability of the proposed MLI is investigated with a 1.3 kW PV system. The closed-loop control strategy ensures the maximum power tracking, dc-link voltage balancing, satisfactory operation of the MLI and injection of clean sinusoidal grid current under any dynamic changes. Comprehensive simulation analysis is carried out considering a 15-level MLI structure. Experimental tests further confirm the practicality of the topological advancement for a PV system under different dynamic conditions. INDEX TERMS Asymmetrical repeating unit, distributed maximum power point tracking, multilevel inverter, photovoltaic (PV) system, reduced components.

Design and Implementation of a Single-Phase 15-Level Inverter With Reduced Components for Solar PV Applications

“…In a real-world scenario, cost and other factors such as several components (N L , N SDC , N SW , N D , N C, TSV/L , THD, Eff & C.F/Nlev) and reliability of these components are also essential. In comparison with other existing topologies [31][32][33][34][35][36][37][38][39][40][41][42] is shown in Table V & Fig.39. It is found out that the number of circuit components is more compared to the proposed MLIs, but because of their better-suited for use regarding the number of sources and lack of difference in terms of harmonic distortion on the lower scale; it is much preferable to use them.…”

“…PARAMETERS COMPARISON WITH SAME EXISTING MLIS[31][32][33][34][35][36][37][38][39][40][41][42] In the proposed 15-level asymmetrical MLI, there are eight switches accordingly gate drive circuits, and three sources with the absence of inductors and capacitors. The blocking voltage across each switch is calculated, and the total standing voltage per level count is calculated and found to be 2, which is significantly less compared with the various topologies.…”

A Survey on Reduced Switch Count Multilevel Inverters

“…Output varies from ±+9nE for 'n' units. V. FUTURE TRENDS Although, many RSC-MLI topologies are reported in open-loop with RL load, a few RSC-MLI configurations are reported for specific applications such as PV [167][168][169], adjustable speed drives [170][171][172][173], power quality [174], FACTS [175], solid-state transformers [176], energy storage [177,178], electric vehicles [179], wireless power transfer [180] and power factor correction [181,182]. While, the RSC-MLI topologies are widely popular in academia from the past decade, they are yet to be penetrated in commercial applications.…”

Design of nine step switched capacitor multilevel inverter and its cascaded extension

“…Recent literature shows the development of converter topologies like T type, Hybrid MLI, 17 Active Neutral Point Clamped (ANPC) inverter, 18,19 and SCMLI 20 by modifying the structures of classical topologies to increase the number of levels, reduce the switch count, and achieve inherent capacitor voltage balancing and voltage boosting. Several hybrid multilevel inverter topologies like Flying Capacitor–Cascaded H Bridge (FC‐CHB), Neutral Point Clamped–Cascaded H Bridge (NPC‐CHB), and Neutral Point Clamped–Flying Capacitor (NPC‐FC) 21–24 developed by combining traditional topologies have not been proved useful for low and medium power application.…”