Clock Skew Minimization in Multi-Voltage Mode Designs Using Adjustable Delay Buffers

Su, Yu-Shih; Hon, Wing-Kai; Yang, Chun-Chuan; Chang, Shih-Chieh; Chang, Yanhong

doi:10.1109/tcad.2010.2061654

Cited by 28 publications

(21 citation statements)

References 15 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Recently, the Post-Silicon Skew Tuning (PST) technique, which can tolerate PVT variations has attracted a lot of attention [5] [6][8] [9]. The main idea of the PST architecture is to dynamically adjust the clock skew after a design is manufactured.…”

Section: Figure 1 a Pst Design With Adbs And Pdsmentioning

confidence: 99%

A robust architecture for post-silicon skew tuning

Kao

Цай

Chang

2011

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

Self Cite

View full text Add to dashboard Cite

Clock skew minimization is important in VLSI design field. Due to the presence of Process, Voltage, and Temperature (PVT) variations, the Post-Silicon Skew Tuning (PST) technique with the ability of tolerating PVT variations has brought a broad discussion. A PST architecture can dynamically minimize the clock skew even after a chip is manufactured. However, testing the variation tolerance ability of a PST architecture is very difficult because the clock skew does not directly affect the functionality of a design. In addition, creating PVT variation in the traditional testing environment is not easy. Unlike most previous works which focus on the implementation and the performance issues of a PST architecture, the objective of this paper is to propose efficient test mechanisms and verify the variation tolerance ability. In addition, we also propose a novel structure to increase the robustness of a PST architecture in case of a manufacturing fault. Our experiment shows that with little overhead, we can achieve robustness.

show abstract

Section: Figure 1 a Pst Design With Adbs And Pdsmentioning

confidence: 99%

A robust architecture for post-silicon skew tuning

Kao

Цай

Chang

2011

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

Self Cite

View full text Add to dashboard Cite

show abstract

“…Because the variation of clock skews in different power modes can be very large, insertion of adjustable delay buffers (ADBs) in the post-silicon process is a widely used methodology to reduce the clock skews in the multiple power modes designs [1][2][3][4][5]. The delay of an ADB is controlled by its control circuit and delay control pins, clock skew variation caused by process variation in different power modes can be tuned by properly replacing some normal clock buffers with ADBs, and assign suitable delay values by properly setting the delay control pins, so that the clock skew constraint in each power mode can be satisfied.…”

Section: Introductionmentioning

confidence: 99%

A window-based methodology for ADBs insertion and clock gating design in multiple power modes

Cheng

2015

2015 International Symposium on Next-Generation Electronics (ISNE)

View full text Add to dashboard Cite

In the low power design of integrated circuits, multiple power modes and clock gating are the two common techniques to reduce dynamic power consumption. In the multiple power modes designs, replacing some of the normal buffers with adjustable delay buffers (ADBs) and assign different delay values in different power modes is one of the promising solutions to satisfy the clock skew constraint, and clock gate splitting is necessary to satisfy the enable timing constraint in clock gating designs. However, both ADBs insertion and gate splitting increase the hardware cost. In this paper, under both the enable timing constraint and clock skew constraint, we propose a skew-window based methodology to reduce the total hardware cost of ADBs and clock gates simultaneously. In comparison with when only ADBs insertion or clock gate splitting technique is applied, experimental results show that our methodology can satisfy the constraints in all the power modes and reduce the hardware cost effectively.

show abstract

“…However, the simple used approach cannot efficiently deal with some specific requirements. Recently, several efficient algorithms [8][9][10][11][12] are proposed to design a buffered clock tree using ADBs for clock skew minimization in a multi-voltage mode design. Su et.…”

Section: Introductionmentioning

confidence: 99%

“…Su et. al [8][9] firstly design a clock tree using ADBs to compensate the delay variation in different power modes. In this design, an efficient algorithm is proposed to heuristically find the feasible locations for ADBs and optimally determine the delay values of the inserted ADBs on each power mode for clock skew minimization.…”

Section: Introductionmentioning

confidence: 99%

“…In this design, an efficient algorithm is proposed to insert ADBs for the minimization of clock skew and buffer area in a multi-voltage mode design. However, the heuristic algorithms [8][9][10][11] cannot minimize the number of the inserted ADBs for clock skew minimization in a multi-voltage mode design. In the ADB assignment for clock skew minimization, Lim et.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs

Yan

Chen

2013

Proceedings of the 23rd ACM International Conference on Great Lakes Symposium on VLSI

View full text Add to dashboard Cite

It is well known that clock skew minimization becomes critical in high-performance VLSI designs. In this paper, the assignment of adjustable delay buffers(ADBs) is applied to minimize the clock skew in a buffered clock tree in a multi-voltage mode design. Given a buffered clock tree, based on the assignment flexibility of the delay value on an ADB, bottom-up ADB assignment is firstly proposed to insert ADBs to minimize the clock skew by assigning the delay values of the inserted ADBs for each power mode. Furthermore, bottom-up ADB elimination is proposed to eliminate the redundant ADBs to minimize the number of the inserted ADBs in a multi-voltage mode design while maintaining the minimized clock skew. Compared with Su's heuristic algorithm and Lim's optimal algorithm, the experimental results show that our proposed algorithm uses less CPU time to reduces 9.3% of the used ADBs and 1.3%~1.6% of the average latency on the average, respectively.

show abstract

Clock Skew Minimization in Multi-Voltage Mode Designs Using Adjustable Delay Buffers

Cited by 28 publications

References 15 publications

A robust architecture for post-silicon skew tuning

A robust architecture for post-silicon skew tuning

A window-based methodology for ADBs insertion and clock gating design in multiple power modes

Assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs

Contact Info

Product

Resources

About