Clock generator using factorial DLL for video applications

Bégueret, Jean-Baptiste; Deval, Yann; Mazouffre, Olivier; Spataro, A.; Fouillat, P.; Benoit,; Mendoza, J.

doi:10.1109/cicc.2001.929826

Cited by 13 publications

(3 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Indeed, the F-DLL offers the reconfigurability of the PLL topology and the very good phase noise performances near to the carrier frequency of the DLL architecture [6]. This article emphasizes on the main block of the retained LO architecture: the Voltage Controlled Delay Line (VCDL).…”

Section: Abstract1mentioning

confidence: 99%

Voltage Controlled Delay Line with Phase Quadrature Outputs for [0.9-4]GHz Factorial Delay Locked Loop Dedicated to Zero-IF Multi-Standard Local Oscillator

Majek

Peslouan

Mariano

et al. 2010

JICS

View full text Add to dashboard Cite

This paper presents the design and the measurement results of a novel Voltage Controlled DelayLine (VCDL) dedicated to an original architecture of Delay Locked Loop (DLL): the Factorial DelayLocked Loop (F-DLL). Based on the multiphase ring oscillator technique, the proposed VCDL offers,among others, two outputs in phase quadrature. These last ones allow the F-DLL to be zero-IF compliantand becomes a good candidate for multi-standard local oscillator. The proposed circuit hasbeen fabricated in a 130nm CMOS-SOI technology from STMicroelectronics. Measurement resultsconfirm the low quadrature phase error of the topology (inferior to 5°) and the ability of the F-DLL tosynthesize the [0.9-4] GHz band, being suited for GSM up to WIMAX applications, while offering veryinteresting performances in term of phase noise and settling time.

show abstract

Section: Abstract1mentioning

confidence: 99%

Voltage Controlled Delay Line with Phase Quadrature Outputs for [0.9-4]GHz Factorial Delay Locked Loop Dedicated to Zero-IF Multi-Standard Local Oscillator

Majek

Peslouan

Mariano

et al. 2010

JICS

View full text Add to dashboard Cite

show abstract

“…The only negative point is the reconfigurability of the architecture. Nevertheless, this drawback can be solved by an original topology which combines the reconfigurability of the PLL and the phase noise performance of the DLL: the Factorial DLL (F-DLL) [6]. This paper focuses on the most critical block of this architecture: the VCDL.…”

Section: Introductionmentioning

confidence: 99%

Voltage controlled delay line with phase quadrature outputs for [0.9-4] GHz F-DLL dedicated to zero-IF multi-standard LO

Majek

Deval

Lapuyade

et al. 2009

Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes

View full text Add to dashboard Cite

This paper presents the design and measurement results of a novel VCDL (Voltage Controlled Delay Line). Based on the multiphase ring oscillator technique, it offers two outputs in phase quadrature. These last ones allow the Factorial DLL (F-DLL) to be zero-IF compliant and so a good candidate for multi-standard LO. The proposed circuit has been fabricated using 130 nm CMOS SOI technology from STMicroelectronics. Measurements confirm the low quadrature phase error of the topology and its ability to synthesize the [0.9-4] GHz band, being suited for GSM up to WIMAX applications.

show abstract

“…The references[1,2,11,13] reported a jitter that is superior to 1ns. Reference[12] reports a jitter of 325ps measured by using a jitter measurement filter having a bandwidth of 65kHz-1.3MHz.…”

mentioning

confidence: 99%

An ADPLL circuit using a DDPS for genlock applications

Calbaza¹,

Cordos²,

Seth-Smith³

et al.

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)

View full text Add to dashboard Cite

This paper presents a fully programmable All-Digital PLL (ADPLL) circuit that is able to synchronize any frequency between 12MHz and 200MHz, with a frequency between 24Hz and 100MHz. This ADPLL circuit uses a Direct Digital Period Synthesizer as a digitally controlled oscillator. The measured jitter at the output is between 184 and 274ps (depending on control parameters). The circuit is implemented in 0.18µm CMOS technology and dissipates 50mW when running at 150MHz.

show abstract

Clock generator using factorial DLL for video applications

Cited by 13 publications

References 9 publications

Voltage Controlled Delay Line with Phase Quadrature Outputs for [0.9-4]GHz Factorial Delay Locked Loop Dedicated to Zero-IF Multi-Standard Local Oscillator

Voltage Controlled Delay Line with Phase Quadrature Outputs for [0.9-4]GHz Factorial Delay Locked Loop Dedicated to Zero-IF Multi-Standard Local Oscillator

Voltage controlled delay line with phase quadrature outputs for [0.9-4] GHz F-DLL dedicated to zero-IF multi-standard LO

An ADPLL circuit using a DDPS for genlock applications

Contact Info

Product

Resources

About