Voltage controlled delay line with phase quadrature outputs for [0.9-4] GHz F-DLL dedicated to zero-IF multi-standard LO

Abstract

This paper presents the design and measurement results of a novel VCDL (Voltage Controlled Delay Line). Based on the multiphase ring oscillator technique, it offers two outputs in phase quadrature. These last ones allow the Factorial DLL (F-DLL) to be zero-IF compliant and so a good candidate for multi-standard LO. The proposed circuit has been fabricated using 130 nm CMOS SOI technology from STMicroelectronics. Measurements confirm the low quadrature phase error of the topology and its ability to synthesize the [0.9-4] GHz band, being suited for GSM up to WIMAX applications.

The P/DLL frequency synthesizer architecture: A native trade-off between stability and wideband frequency generation

“…This error generates multiple close-in spurious, surrounding the carrier frequency. Those spurious are equally spaced by the reference frequency, which is a moderately low frequency when compared to the carrier, forbidding subsequent filtering of any kind [5]. Because of this dormant drawback, the DLL has not been successful as a potential replacement of narrow band PLL in the telecommunication industry.…”