Clock distribution networks for 3-D ictegrated Circuits

Abstract

Three-dimensional (3-D) integration is an important technology that addresses fundamental limitations of on-chip interconnects. Several design issues related to 3-D circuits, such as multi-plane synchronization, however, need to be addressed. A comparison of three 3-D clock distribution network topologies is presented in this paper. Experimental results of a 3-D test circuit manufactured by the MIT Lincoln Laboratories are also described. Successful operation of the 3-D test circuit at 1.4 GHz is demonstrated. Clock skew and power dissipation measurements for the different clock topologies are also provided.

Post Silicon Management of On-Package Variation Induced 3D Clock Skew

“…Temperature dependent clock skew control and power analysis for H-tree based clock network topologies are presented in the works [4][5][6]. Mondal et al [4] proposed a thermally adaptive clocking scheme to reduce the temperature dependent clock skew.…”

“…Arunachalam and Burleson [5] proposed a low power clock design by using a separate layer for the clock network. Pavlidis, Savidis, and Friedman [6] compared clock skew and power consumption for various H-tree based clock network topologies with real measurement data.…”

Design and Testing Strategies for Modular 3-D-Multiprocessor Systems Using Die-Level Through Silicon Via Technology

“…The clock distribution in 3-D-ICs is a complex and challenging task, as presented by Pavlidis et al in [34]. The synchronization of sequential elements located on multiple planes by the same clock signal underlines the importance of controlling the clock skew.…”

Skew variability in 3-D ICs with multiple clock domains

“…In this case, the correlation of WID variations is modeled by (7). As reported in the column "Multi-correlation" in Table II, the behavior of the investigated clocking schemes differs from the other correlation models.…”

“…The focus of this paper is on the effect of process variations on the clock skew of potential 3-D synchronization architectures with multiple clock domains. The case studies include regular clock networks that globally distribute the clock signal in a 3-D stack [6], [7]. The proposed model can also be used to analyze synthesized 3-D clock trees [8], [9].…”