Clock and data recovery circuit for 10-Gb/s asynchronous optical packets

ARTEMIS: 40-gb/s all-optical self-routing node and network architecture employing asynchronous bit and packet-level optical signal processing

“…9, the eye diagrams at the output of the switching matrix exhibit less timing jitter when compared to the eye diagrams of the incoming asynchronous packets. This effective retiming is achieved by the header/payload separation subsystem that exhibits regenerative properties, since the incoming packets are sampled with the retimed extracted clock packets [19]. Fig.…”

“…These optical logic elements are suitable for a high-speed signal processing and they have already been established as the fundamental building blocks of all-optical switching nodes [11]. In this context, all-optical gates have been used as core elements performing a diversity of network functionalities, such as wavelength conversion [12], data regeneration [13], [14], clock recovery [15], [16], header from payload separation [17], [18], header matching [7], and data recovery [19].…”

Optical Power Limiter Using a Saturated SOA-Based Interferometric Switch

“…Minor variations between the two curves, like the threshold for obtaining the "flat" response, are presumably due to the nonnegligible internal losses of the SOA. It is worth mentioning that power-limiting is obtained while the switch still exhibits 2R regenerative properties [7], taking advantage of the typical sinusoidal transfer function shape below the threshold value. It should be noted that the use of different interferometric structures for the theoretical and experimental analysis, respectively, does not impair the conclusions of this study or the validity of the agreement, since both configurations rely on the same principle of operation due to their interferometric arrangement.…”

“…If electronic circuitry is a guide, power limiting devices, for example, are close relatives to active switching elements as their operation relies on the saturation of the transistors, and their optical high-speed analogue versions would certainly extend the optical signal processing application vistas [2] and improve their performance [3]. So far, SOA-based switches with enhanced input power dynamic range have been presented [4], [5], whereas more recently, we have proposed the use of saturated SOAbased optical gates to demonstrate novel functional subsystems for optical packet switching applications [6], [7]. However, no detailed analysis of the gate's operational potential as an optical power limiter has been presented so far.…”

On the Feasibility of 320 Gb/S All-Optical and Gate Using Quantum-Dot Semiconductor Optical Amplifier-Based Mach-Zehnder Interferometer

“…In particular the AND gate is indispensable for achieving this goal as it is involved in the accomplishment of numerous tasks in the optical domain both in fundamental and system-oriented level, such as buffering [2], address comparison [3], add-drop multiplexing [4], packet clock and data recovery [5], packet header and payload separation [6], binary pattern recognition [7], binary counting [8], analog-to-digital conversion [9], digital encoding and comparison [10], data regeneration [11], waveform sampling [12], half addition [13], multiplication [14], construction of other logic gates [15] and of combinational logic circuits [16]. Given its important, multi-lateral role the AND gate has attracted intense research interest and among the technological options that exist for its implementation those that exploit a semiconductor optical amplifier (SOA) are well established [17].…”