Cleaning of High Aspect Ratio STI Structures for Advanced Logic Devices by Implementation of a Surface Modification Drying Technique

Sebaai, Farid; Vereecke, Guy; Xu, Xiumei; Baudot, S.; Amemiya, Fumihiro; Komori, Kana; Holsteyns, Frank

doi:10.4028/www.scientific.net/ssp.282.190

Cited by 7 publications

(10 citation statements)

References 5 publications

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“…The drying observation of the HAR structures with aspect ratio of 13.3 using the C1 and C8 confirmed that it is not important to obtain high water repellency, but it is very important to obtain lower surface free energy, as shown in Figure 40 [243]. The alkyl group surface can be easily removed by oxidative or reductive plasma strip by means of N2O or N2/H2 plasmas [244]. Farid et al demonstrated the STI structures with 9 nm CD, 25 nm pitch, and 160 nm fin height [244].…”

Section: Wet Cleaningmentioning

confidence: 85%

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State of the Art and Future Perspectives in Advanced CMOS Technology

et al. 2020

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The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today’s transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according to Moore’s law. This article presents a review of new architectures, simulation methods, and process technology for nano-scale transistors on the approach to the end of ITRS technology. The discussions cover innovative methods, challenges and difficulties in device processing, as well as new metrology techniques that may appear in the near future.

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Section: Wet Cleaningmentioning

confidence: 85%

“…The alkyl group surface can be easily removed by oxidative or reductive plasma strip by means of N2O or N2/H2 plasmas [244]. Farid et al demonstrated the STI structures with 9 nm CD, 25 nm pitch, and 160 nm fin height [244]. However, silicon oxide powder samples treated with the C1 and C8 showed different results.…”

Section: Wet Cleaningmentioning

confidence: 99%

State of the Art and Future Perspectives in Advanced CMOS Technology

et al. 2020

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“…Copper-reflow is a potential gap-fill solution as it eliminates the copper seed overhang formation and creates the perfect bottom-up fill to replace electrochemical plating (ECP). Beyond advanced 7 nm technology, Samsung adopted a "Cu reflow" process improving copper fill ability in smallest design features as part of Back End of Line (BEOL) contacts and metal islands, ensuring manufacturability by aggressive chip scaling [298]. Figure 32 shows the flow diagram for the Cu reflow process on Co liner and the corresponding improvement in electromigration (EM).…”

Section: Metal Materials Interconnectmentioning

confidence: 99%

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

Radamson,

Miao,

Zhou

et al. 2024

Nanomaterials

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After more than five decades, Moore’s Law for transistors is approaching the end of the international technology roadmap of semiconductors (ITRS). The fate of complementary metal oxide semiconductor (CMOS) architecture has become increasingly unknown. In this era, 3D transistors in the form of gate-all-around (GAA) transistors are being considered as an excellent solution to scaling down beyond the 5 nm technology node, which solves the difficulties of carrier transport in the channel region which are mainly rooted in short channel effects (SCEs). In parallel to Moore, during the last two decades, transistors with a fully depleted SOI (FDSOI) design have also been processed for low-power electronics. Among all the possible designs, there are also tunneling field-effect transistors (TFETs), which offer very low power consumption and decent electrical characteristics. This review article presents new transistor designs, along with the integration of electronics and photonics, simulation methods, and continuation of CMOS process technology to the 5 nm technology node and beyond. The content highlights the innovative methods, challenges, and difficulties in device processing and design, as well as how to apply suitable metrology techniques as a tool to find out the imperfections and lattice distortions, strain status, and composition in the device structures.

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“…One such problem is the collapse of nanostructures due to capillary interactions during evaporation of cleaning solutions, a process that is exacerbated by increasing miniaturization of semiconductor devices and consequent weakening of nanostructures. − The collapse of nanostructures destroys their expected functions, so countermeasures are essential. To solve this problem, new drying techniques to prevent collapse have been developed, such as the addition of an auxiliary substrate, the use of a liquid with a low surface tension to control the wettability of the substrate, , the reduction of capillary forces by electromagnetic-wave irradiation, or the elimination of capillary forces by drying without the involvement of a liquid phase through sublimation or supercriticality. , However, no effective solution has yet been established, and this problem might be one factor that makes it impossible to maintain Moore’s law.…”

Section: Introductionmentioning

confidence: 99%

Liquid-Cell Transmission Electron Microscopy Observation of Two-Step Collapse Dynamics of Silicon Nanopillars on Evaporation of Propan-2-ol: Implications for Semiconductor Integration Density

Sasaki

Yamazaki

Kimura

2022

ACS Appl. Nano Mater.

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Miniaturization of semiconductor devices has made structures more fragile, leading to potential collapses due to capillary forces during drying after wet cleaning. This has hampered the integration of transistors according to Moore's law. We have developed a method for preparing nanopillars in a liquid cell and have successfully observed their collapse by means of a crosssectional view in transmission electron microscopy. The dynamics of collapse as a result of capillary interactions involve two steps. First, the nanopillars collapse due to an imbalance in capillary forces caused by a difference in liquid levels at the gas−liquid interface. Second, a liquid pool formed between nanopillars maintains the collapsed state of the nanopillars through surface tension. The nanopillars recover on reimmersion in the liquid after the collapse. This method is effective, and is expected to contribute to the continued development of miniaturization and three-dimensionality of semiconductors.

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Cleaning of High Aspect Ratio STI Structures for Advanced Logic Devices by Implementation of a Surface Modification Drying Technique

Cited by 7 publications

References 5 publications

State of the Art and Future Perspectives in Advanced CMOS Technology

State of the Art and Future Perspectives in Advanced CMOS Technology

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

Liquid-Cell Transmission Electron Microscopy Observation of Two-Step Collapse Dynamics of Silicon Nanopillars on Evaporation of Propan-2-ol: Implications for Semiconductor Integration Density

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