Classification for 2D-DCTs and a new architecture with distributed arithmetic

Wolter, S.; Birreck, D.; Laur, R.

doi:10.1109/iscas.1991.176736

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Multipliers1

E N -D F T ( ( ( B + L ) K I ) ) B~~~~~z + I ) K L ) ) Z1

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2011

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Cited by 5 publications

(2 citation statements)

References 16 publications

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“…An analysis finds that the DA architecture provides higher speed than a hardwired multiplier but also dissipates more power [34]. The advantages of the DA make it a popular choice for high-speed, low area implementations [12] [36].…”

Section: Multipliersmentioning

confidence: 99%

On the low-power design of DCT and IDCT for low bit-rate video codecs

August

Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No.01TH8558)

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Section: Multipliersmentioning

confidence: 99%

On the low-power design of DCT and IDCT for low bit-rate video codecs

August

Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No.01TH8558)

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“…1 DlT/DCT conversion and the required additions for one output can be executed as inner products. The inner products are realized with distributed arithmetic @A) using the modifiered ROM accumulator modules (MRACs) presented in [2]. The structure of an MRAC is shown in figure 2.…”

Section: E N -D F T ( ( ( B + L ) K I ) ) B~~~~~z + I ) K L ) ) Zmentioning

confidence: 99%

Parallel architectures for 8*8 discrete cosine transforms

Wolter

Birreck

Heine

et al.

[Proceedings] 1992 IEEE International Symposium on Circuits and Systems

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This paper addresses the design of parallel architectures for computing the 8x8 Discrete Cosine Transform (DCT). It concentrates on direct methods, which avoid a row-column decomposition.Two novel multiplier-free parallel architectures for high-speed 8x8 DCT calculation are proposed. The first architecture, which uses polynomial transforms, is compared with a second architecture, which computes the DCT via the Walsh-Hadamard Transform (WHT). Both architectures achieve a high degree of parallelism and regularity. The proposed architectures are designed for HDTV sampling rates and can be emaently realized in CMOS technology.

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Power comparison of flow-graph and distributed arithmetic based DCT architectures

Kuhlmann

Parhi²

Conference Record of Thirty-Second Asilomar Conference on Signals, Systems and Computers (Cat. No.98CH36284)

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Classification for 2D-DCTs and a new architecture with distributed arithmetic

Cited by 5 publications

References 16 publications

On the low-power design of DCT and IDCT for low bit-rate video codecs

On the low-power design of DCT and IDCT for low bit-rate video codecs

Parallel architectures for 8*8 discrete cosine transforms

Power comparison of flow-graph and distributed arithmetic based DCT architectures

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