Class D CMOS power amplifier with on/off logic for a multilevel outphasing transmitter

Martelius, Mikko; Stadius, Kari; Lemberg, Jerry; Nieminen, Tero; Roverato, Enrico; Kosunen, Marko; Ryynänen, Jussi; Anttila, Lauri; Valkama, Mikko

doi:10.1109/iscas.2016.7527339

Cited by 10 publications

(18 citation statements)

References 7 publications

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“…The output-stage transistor sizes were chosen such that their on-resistances do not cause significant output-voltage saturation at the peak output power. Building on our analysis in [6], this means that the vast majority of power loss in the PA units occurs due to the charging and discharging of the relatively large drain-source capacitances of the output transistors. By assuming that other losses are negligible, we can thus derive a simple efficiency model in which the loss in each active PA unit, P loss , is constant and independent of output power.…”

Section: Tri-phasing Power Amplifiermentioning

confidence: 99%

“…This helps to describe some of the factors that affect the common-mode and differential current components. As (6) shows, I CM is directly defined by the sum of PA-unit output currents. Those currents depend partly on the characteristics of the power combiner, as will be shown in a later part of this analysis.…”

Section: Analysis Of Pa Supply and Ground Ripplementioning

confidence: 99%

“…5 depicts the schematic of a single PA unit featuring a cascoded class-D output stage. In order to switch the output stage on and off according to the signal A, the XOR and NAND gates construct the desired signals in both "on" and "off" states in a manner that allows constant bias voltages [6], [9]. This solution enables multilevel operation with a relatively high 3.6-V supply voltage in an integrated system, where all PA input signals are generated in the 1.0-V domain.…”

Section: Tri-phasing Power Amplifiermentioning

confidence: 99%

“…In these measurements, the peak-to-average power ratio (PAPR) is reduced with iterative clipping and filtering, which increases 1. 6 1 .62 1.64 1.66 1.68 1.7 1.72 1.74 1.76 1 the output power with virtually no effect on the ACLR, while gradually increasing the EVM. To maximize output power and efficiency, we chose the lowest PAPR that maintains an EVM of at most 8% in each carrier, in accordance with LTE specifications.…”

Section: B Measurements With Modulated Signalsmentioning

confidence: 99%

“…A previously proposed solution for improving the back-off efficiency is multilevel outphasing, in which the output amplitude is modulated by discrete amplitude levels in addition to a phase offset [3], [4]. In our earlier work, we have developed new circuit solutions for phase modulators [5] and PAs [6] intended for highly integrated wideband multilevel outphasing transmitters [7]. However, while analyzing the characteristics of multilevel outphasing, we have found that amplitude-level transitions inherently cause discontinuities in the harmonic content of the combined output signal [8].…”

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confidence: 99%

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A Class-D Tri-Phasing CMOS Power Amplifier With an Extended Marchand-Balun Power Combiner

Martelius

Ryynänen

Stadius

et al. 2020

IEEE Trans. Microwave Theory Techn.

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This paper presents a power amplifier (PA) design, which consists of eight class-D PA units on a single 28-nm CMOS die and a coupled-line power combiner on printed circuit board (PCB). The PA utilizes tri-phasing modulation, which combines polar and outphasing components in a way that eliminates linearity-degrading effects of multilevel outphasing while maintaining the back-off efficiency. Each PA unit contains a cascoded output stage with a 3.6-V supply voltage, and multilevel operation is enabled by on/off logic circuitry. Our analysis shows that the choice of power-combiner type is vital for reducing PA supply and ground ripple and thus ensuring reliable operation. Accordingly, the power combiner is implemented with extended Marchand baluns, which consist of input transmission lines and coupled-line sections. Unlike the original Marchand balun, our new topology is feasible for implementation under the layout restrictions caused by the multiple-unit PA on a single die. Measurement results show the PA achieving a peak output power of 29.7 dBm with a 34.7% efficiency, and operation with aggregated LTE signals at 1.7-GHz carrier frequency is verified with bandwidths up to 100 MHz.

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Section: Tri-phasing Power Amplifiermentioning

confidence: 99%

Section: Analysis Of Pa Supply and Ground Ripplementioning

confidence: 99%

Section: Tri-phasing Power Amplifiermentioning

confidence: 99%

Section: B Measurements With Modulated Signalsmentioning

confidence: 99%

mentioning

confidence: 99%

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A Class-D Tri-Phasing CMOS Power Amplifier With an Extended Marchand-Balun Power Combiner

Martelius

Ryynänen

Stadius

et al. 2020

IEEE Trans. Microwave Theory Techn.

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Delay Mismatches Analysis for Multi-level Outphasing Digital Transmitters

Chen

Wei

Zhu

2022

2022 IEEE 22nd International Conference on Communication Technology (ICCT)

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A 30-GHz Switched-Capacitor Power Amplifier for 5G SoCs

Saleem

Stadius

Kosunen

et al. 2020

2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)

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Switched-capacitor power amplifier has gained popularity within the radio frequency integrated circuit community, since it is CMOS compatible offering high integration density and good performance particularly in terms of linearity. In this paper we present a study on the use of switched-capacitor power amplifier at millimeter-wave frequency range. We identify the major design challenges in this paper, and demonstrate the feasibility of switched-capacitor power amplifier with a 30-GHz design case. Our analysis describes the effects of power amplifier device parasitics and their contribution to dynamic power consumption, revealing that these are a major factor in degradation of switched capacitor power amplifier efficiency at millimeter waves. Two circuits, one for 3 GHz and the other for 30 GHz, were designed and simulated with 28-nm bulk CMOS technology. At 3 GHz, the designed switched capacitor power amplifier structure with 6-bit resolution features maximum output power of 19.4 dBm and efficiency of 59% whereas the output power of 18.6 dBm with 21% efficiency is achieved at 30 GHz. The switched-capacitor power amplifier preserves its good linearity at higher frequencies as well, and our design demonstrates an adjacent channel leackage ratio of-34.4 dB at 30 GHz for a 100-MHz OFDM-modulated signal.

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Class D CMOS power amplifier with on/off logic for a multilevel outphasing transmitter

Cited by 10 publications

References 7 publications

A Class-D Tri-Phasing CMOS Power Amplifier With an Extended Marchand-Balun Power Combiner

A Class-D Tri-Phasing CMOS Power Amplifier With an Extended Marchand-Balun Power Combiner

Delay Mismatches Analysis for Multi-level Outphasing Digital Transmitters

A 30-GHz Switched-Capacitor Power Amplifier for 5G SoCs

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