CIXB-1: combined input-one-cell-crosspoint buffered switch

Rojas‐Cessa, Roberto; Oki, Eiji; Jing, Zhimin; Chao, H. Jonathan

doi:10.1109/hpsr.2001.923655

Cited by 174 publications

(161 citation statements)

References 14 publications

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“…Therefore, the increasing of k negligibly affects the results. As in [10], the size of k needs to be determined by the RT time. As the size of k does not affect the performance of RR-AF, k is assigned the value of one cell, (i.e., k = 1), in the remainder of the paper, unless otherwise stated.…”

Section: Rr-af Was Simulated With Different Sizes Of Kmentioning

confidence: 99%

“…The round trip (RT ) time, as in [10], is defined as the sum of the delays of the input arbitration (IA), the transmission of a cell from an input to the crossbar (d1), the output arbitration (OA), and the transmission of the flow-control information back from the crossbar to the input (d2). Figure 1 shows an example of RT for input 0 by showing the transmission delays for d1 and d2, and arbitration times, IA and OA.…”

Section: Combined Input-crosspoint Buffered Switch Modelmentioning

confidence: 99%

“…However, schemes based on round-robin selection have not been shown to provide nearly 100% throughput under nonuniform traffic patterns with a buffered crossbar that have crosspoint buffers of small size. For example, it has been shown that a switch using RR needs a large crosspoint buffer to provide high throughput under admissible unbalanced traffic [17], where the unbalanced traffic model is a nonuniform traffic pattern [10]. This large buffer can make the implementation of a switch costly.…”

Section: Introductionmentioning

confidence: 99%

“…Furthermore, it has been shown that a CICB switch using one-cell crosspoint buffers, a simple round-robin arbitration (RR) scheme for input and output arbitration, and a credit-based flow control provide 100% throughput for uniform traffic [10]. However, as actual traffic may present nonuniform distributions, it is necessary to provide arbitration schemes that provide 100% throughput for admissible traffic.…”

Section: Introductionmentioning

confidence: 99%

“…The size of CPB i, j , k, is indicated by the number of cells that can be stored. A credit-based flow-control mechanism indicates to input i whether CPB i, j has room available for a cell or not, as described in [10]. For this flow-control mechanism, there is a credit counter in each VOQ that counts the number of outstanding cells (i.e., cells sent to CPB).…”

Section: Introductionmentioning

confidence: 99%

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Round-Robin Selection with Adaptable Frame-Size for Combined Input-Crosspoint Buffered Packet Switches

Rojas‐Cessa¹

2006

IEICE Transactions on Communications

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SUMMARY Combined input-crosspoint buffered (CICB) switches relax arbitration timing and provide high-performance switching for packet switches with high-speed ports. It has been shown that these switches, with one-cell crosspoint buffer and round-robin arbitration at input and output ports, provide 100% throughput under uniform traffic. However, under admissible traffic patterns with nonuniform distributions, only weight-based selection schemes are reported to provide high throughput. This paper proposes a round-robin based arbitration scheme for a CICB packet switch that provides 100% throughput for several admissible traffic patterns, including those with uniform and nonuniform distributions, using one-cell crosspoint buffers and no speedup. The presented scheme uses adaptable-size frames, where the frame size is determined by the traffic load.

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Section: Rr-af Was Simulated With Different Sizes Of Kmentioning

confidence: 99%

Section: Combined Input-crosspoint Buffered Switch Modelmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Round-Robin Selection with Adaptable Frame-Size for Combined Input-Crosspoint Buffered Packet Switches

Rojas‐Cessa¹

2006

IEICE Transactions on Communications

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A high‐performance switch architecture based on mesh of trees

Chang

Zheng

2012

Int J Communication

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With emergence of various new Internet-enabled devices, such as tablet PCs or smart phones along with their own applications, the traffic growth rate is getting faster and faster these days and demands more communication bandwidth at even faster rate than before. To accommodate this ever-increasing network traffic, even faster Internet routers are required. To respond for these needs, we propose a new mesh of trees based switch architecture, called MOT S.N / switch. In addition, we also propose two more variations of MOT S.N / to further improve it. MOT S.N / is inspired by crossbar with crosspoint buffers. It forms a binary tree for each output line, where each gridpoint buffer ‡ is a leaf node and each internal node is 2-in 1-out merge buffer § emulating FIFO queues. Because of this FIFO characteristic of internal buffers, MOT S.N / ensures QoS like FIFO output-queued switch. The root node of the tree for each output line is the only component connected to the output port where each cell is transmitted to output port without any contention. To limit the number of buffers in MOT S.N / switch, we present one of its improved (practical) variations, IMOTS.N / switch, as well. For IMOTS.N / switch architecture, sizes of the buffers in the fabric are limited by a certain amount. As a downside of IMOTS.N /, however, every cell should go through log 2 N C 1 number of buffers in the fabric to be transmitted to the designated output line. Therefore, for even further improvement, IMOTS.N / with cut-through, denoted as IMOTS-C T .N /, is also proposed in this paper. In IMOTS-C T .N / switch, the cells can cut through one or more empty buffers to be transferred from inputs to outputs with simple 1 or 2 bit signal exchanges between buffers. We analyze the throughput of MOT S.N /, IMOTS.N /, and IMOTS-C T .N / switches and show that they can achieve 100% throughput under Bernoulli independent and identically distributed uniform traffic. Our quantitative simulation results validate the theoretical analysis. ‡ Because the fabric of MOT S.N / switch is not pure crossbar, we call the buffers in the same location in pure crossbar gridpoint buffers. Details will be presented in the following sections. § 2-in 1-out merge buffer can accommodate two memory writes and one memory read simultaneously by using its modularized architecture [31].According to the location of buffers, various crossbar switch architectures have been proposed and studied. The examples of unbuffered crossbar switches are input-queued (IQ), output-queued (OQ), and combined input-queued and output-queued (CIOQ) switches. In OQ switch, cell are forwarded to and queued at output ports without any intermediate delay. As a result, it is very powerful to provide QoS. However, large-sized OQ switch is practically infeasible and remains in theory because the memory speed should be N times faster than the line rate, where N is the size of the switch.In IQ switch, packets are queued at input ports first as they arrive to the switch. For this switch architecture, memory spe...

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Packet Switch with Internally Buffered Crossbars

Guo

Rojas‐Cessa

Ansari

High-Performance Packet Switching Architectures

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The increasing demand for higher data rates on the Internet requires routers that deliver high performance for high-speed connections. While output-buffered switches are known for their limited scalability, input-buffered (IB) switches have been of interest for research and commercialization. However, IB switches may not be able to keep up with the increasing data rates as optical technology advances rapidly. To keep up with the increasing data rates, switches based on internally buffered crossbars are considered a feasible solution for the next generation packet switches. The cost associated with internally buffered crossbar switches is tied to the addition of buffers to the crosspoint elements. Here, we present an overview of several internally buffered crossbar switches and their selection schemes. Furthermore, we discuss the properties of the different approaches to internally buffered packet switches.

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CIXB-1: combined input-one-cell-crosspoint buffered switch

Cited by 174 publications

References 14 publications

Round-Robin Selection with Adaptable Frame-Size for Combined Input-Crosspoint Buffered Packet Switches

Round-Robin Selection with Adaptable Frame-Size for Combined Input-Crosspoint Buffered Packet Switches

A high‐performance switch architecture based on mesh of trees

Packet Switch with Internally Buffered Crossbars

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