A high‐performance switch architecture based on mesh of trees

Abstract

With emergence of various new Internet-enabled devices, such as tablet PCs or smart phones along with their own applications, the traffic growth rate is getting faster and faster these days and demands more communication bandwidth at even faster rate than before. To accommodate this ever-increasing network traffic, even faster Internet routers are required. To respond for these needs, we propose a new mesh of trees based switch architecture, called MOT S.N / switch. In addition, we also propose two more variations of MOT S.N / to further improve it. MOT S.N / is inspired by crossbar with crosspoint buffers. It forms a binary tree for each output line, where each gridpoint buffer ‡ is a leaf node and each internal node is 2-in 1-out merge buffer § emulating FIFO queues. Because of this FIFO characteristic of internal buffers, MOT S.N / ensures QoS like FIFO output-queued switch. The root node of the tree for each output line is the only component connected to the output port where each cell is transmitted to output port without any contention. To limit the number of buffers in MOT S.N / switch, we present one of its improved (practical) variations, IMOTS.N / switch, as well. For IMOTS.N / switch architecture, sizes of the buffers in the fabric are limited by a certain amount. As a downside of IMOTS.N /, however, every cell should go through log 2 N C 1 number of buffers in the fabric to be transmitted to the designated output line. Therefore, for even further improvement, IMOTS.N / with cut-through, denoted as IMOTS-C T .N /, is also proposed in this paper. In IMOTS-C T .N / switch, the cells can cut through one or more empty buffers to be transferred from inputs to outputs with simple 1 or 2 bit signal exchanges between buffers. We analyze the throughput of MOT S.N /, IMOTS.N /, and IMOTS-C T .N / switches and show that they can achieve 100% throughput under Bernoulli independent and identically distributed uniform traffic. Our quantitative simulation results validate the theoretical analysis. ‡ Because the fabric of MOT S.N / switch is not pure crossbar, we call the buffers in the same location in pure crossbar gridpoint buffers. Details will be presented in the following sections. § 2-in 1-out merge buffer can accommodate two memory writes and one memory read simultaneously by using its modularized architecture [31].According to the location of buffers, various crossbar switch architectures have been proposed and studied. The examples of unbuffered crossbar switches are input-queued (IQ), output-queued (OQ), and combined input-queued and output-queued (CIOQ) switches. In OQ switch, cell are forwarded to and queued at output ports without any intermediate delay. As a result, it is very powerful to provide QoS. However, large-sized OQ switch is practically infeasible and remains in theory because the memory speed should be N times faster than the line rate, where N is the size of the switch.In IQ switch, packets are queued at input ports first as they arrive to the switch. For this switch architecture, memory spe...