Circuit Switched Run-Time Adaptive Network-on-Chip for Image Processing Applications

Abstract

Since the 1990s reusable functional blocks, well known as IP-Cores, have been integrated on one silicon die. These Systems-on-Chip (SoC) used a bus-based system for intermodule communication. Technology, performance and flexibility issues require the introduction of a novel communication system called Network-on-Chip (NoC). Around 1999 this method was introduced and since then has been investigated by several research groups with the aim to connect different IP-Cores through an effective, flexible and scalable communication network. Exploiting the flexibility of FPGAs, the run-time adaptivity through run-time reconfiguration, opens a new area of research by considering dynamic and partial reconfiguration. Since software parts of an electronic system can also be included into reconfigurable hardware by integration of IP-based microcontrollers, the reconfigurable architecture provides a flexible, multi-adaptive heterogeneous platform for HW / SW Co-designs. This paper presents an approach for exploiting dynamic and partial reconfiguration with Xilinx Virtex-II FPGAs for an adaptive circuit switched Networkon-Chip and the related techniques for adapting the system during run-time to the requirements of the presented image processing application.

A self adaptive interfacing concept for consumer device integration into automotive entities

“…To have more flexible bus connections it has been shown that data flow can be steered by using look-up-tables (LUTs) based routing [5]. Thus it is possible to implement a switch box which can change the dataflow by writing one configuration frame.…”

“…To be able to set multilayer bus connections during runtime, the partial bitstreams do not include any connection to any of the layers. This connection is established during configuration by changing the corresponding bits of the bitstream on the fly as shown in principle in [5]. Reconfiguration of the bus structure can be realized through Read-Modify-Writeback method as presented in [14] (see II).…”

Key Research Issues for Reconfigurable Network-on-Chip

“…The first solution addressed in [5] is called circuit switched. This approach allows modules, which are willing to communicate, to establish a physical connection by setting some multiplexers on the communication links.…”

Run-time reconfigurable adaptive multilayer network-on-chip for FPGA-based systems

“…Actual research work in this area shows, that the switched based network integrated on Xilinx FPGAs, can be reconfigured in the time frame of 20µs. Certainly this time differs with the size of the selected FPGA as described in [12]. In [12] the registers controlling the switches of the network are aligned in a CLB row of the FPGA.…”

“…Certainly this time differs with the size of the selected FPGA as described in [12]. In [12] the registers controlling the switches of the network are aligned in a CLB row of the FPGA. Therefore the described approach can be used by exploiting the dynamic and partial reconfiguration feature of the Xilinx FPGA.…”