Circuit Reliability Analysis Using Signal Reliability Correlations

Fast and Accurate SER Estimation for Large Combinational Blocks in Early Stages of the Design

“…The proposal in [36] extends the work in CEP by using a SAT solver to compute signal probabilities in reconvergent nodes, which reduce the accuracy of the correlation rules. Cai and Chen also propose to use signal correlations in [37], where they introduce a new set of rules that achieve excellent accuracy. The probabilistic techniques on these works, however, only demonstrate their feasibility on small-sized circuits and the required analysis to run them would require a significant analysis time for medium and large-sized circuits.…”

“…The first one is the lack of a framework capable of computing all three masking factors in a holistic way, which impacts the correctness of those works. The techniques presented in [31], [33], [37], [38] and [39] only take into account logical masking. On the other hand, approaches such as [15], [27], [40], [41] or [36] do not compute the electrical masking effect, while [42] and [2] overlook the logical masking effect.…”

“…0] which correspond to the probability that, given a strike, the output at g i transitions, respectively, from 0 to 1 and from 1 to 0. [31], [37], [38], [39] [2], [15], [27], [40] [22], [24], [43] Every element g i of G has associated a rise time t r and a fall time t f , which correspond to the slopes of the output pulse generated when g i is struck (from 10 to 90 percent of V dd and from 90 to 10 percent of V dd , respectively). Every element g i of G has associated a propagation delay d, the minimum switching delay among all input combinations of the gate.…”