Circuit-level simulation of TDDB failure in digital CMOS circuits

Aging-Aware Instruction Cache Design by Duty Cycle Balancing

“…By further combining the bitflipping/complementing scheme for the invalid cachelines, our AAIC design can reduce the average stress duty cycle ratio to 51.7% for the entire instruction cache, as shown in Figure 6. Previous study has shown that the gate-oxide failure probability is proportional to the device stress time [4]. Therefore, we can expect a similar MTTF (mean time to failure) improvement for the instruction cache.…”

“…The increased current density and temperature in future devices will further accelerate the degradation. Bias temperature instability (BTI), hot-carrier injection, and gate-oxide wearout are the primary aging mechanisms for CMOS devices [2][3] [4]. The negative bias temperature instability (NBTI) for pMOS devices are one of the most prominent and persistent threats for future technologies.…”

Design of 2xVDD-tolerant mixed-voltage I/O buffer against gate-oxide reliability and hot-carrier degradation

“…For the impracticality to insert pads for measuring the real voltage difference for certain transistors in the I/O buffer, the help of simulation is necessary. Since the researches on device-level reliability problem have been done by many papers as [10,[16][17][18][19], this work only provides simulated results, which are reasonable proofs to foresee that this work has better reliability performance with steady state and transient considerations. …”

“…To ensure the circuits at least alive after continually overstress under certain worst-case circuit operating condition [13], transistors operating within 1-1.1 times of normal supply voltage in the I/O or driver circuits become a practical and common design principle [13][14][15]. Degradations caused by hot carriers and gate-oxide overstress are actually time dependent issues as discussed in [16][17][18][19], which are also functions of the probability for the happening of overstress condition during circuit operations. When the drain voltage of NMOS device is larger than its gate voltage (for the overstress condition in the following circuits under discussion), the drain avalanche hot carrier injection (DAHC) becomes an important mechanism [5].…”

Design of Charge Pump Circuit With Consideration of Gate-Oxide Reliability in Low-Voltage CMOS Processes

“…Gate-oxide reliability is a time-dependent issue [24], [25]. The time period during the voltage overstress on the gate oxide is accumulated to induce the oxide breakdown.…”