Design of 2xVDD-tolerant mixed-voltage I/O buffer against gate-oxide reliability and hot-carrier degradation

Tsai, Hsun-Heng; Ker, Ming‐Dou

doi:10.1016/j.microrel.2009.09.004

Cited by 3 publications

(3 citation statements)

References 25 publications

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“…In order not to stress the transistors, the supply voltage level has to be lowered as well. In an electronic system, however, an integrated circuit (IC) implemented in a deep sub‐micron CMOS process may have to interface with other peripheral components and/or ICs operating at much higher supply voltage levels, for example, 3.3 and 5.0 V. Interfacing with these ICs requires special type of I/O circuits that can protect the deep sub‐micron CMOS transistors from the intolerable voltage stress; otherwise, the lifetime of the deep sub‐micron CMOS transistors can be severely shortened . Although the circuit techniques in are useful to protect transistor from over‐voltage stress, there is no report on an I/O circuit in 28 nm CMOS process that can tolerate up to 5.25 V voltage stress to the authors' best knowledge.…”

Section: Introductionmentioning

confidence: 99%

A 5.25‐V‐tolerant bidirectional I/O circuit in a 28‐nm CMOS process

Ahn

Park²,

Yoo

2014

Circuit Theory & Apps

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A 5.25-V-tolerant bidirectional I/O circuit has been developed in a 28-nm standard complementary metal-oxide-semiconductor (CMOS) process with only 0.9 and 1.8 V transistors. The transistors of the I/O circuit are protected from over-voltage stress by cascode transistors whose gate bias level is adaptively controlled according to the voltage level of the I/O pad. The n-well bias level of the p-type metal-oxide-semiconductor transistors of the I/O circuit is also adapted to the voltage level of the I/O pad to prevent any junction leakage. The 5.25-V-tolerant bidirectional I/O circuit occupies 40 μm × 170 μm of silicon area. KEY WORDS: I/O circuit; voltage stress; bidirectional I/O; CMOS 2. 5.25-V-TOLERANT BIDIRECTIONAL I/O CIRCUIT IN 28-NM CMOS TECHNOLOGYThe bidirectional I/O circuit is targeted to be applied in a system on chip (SoC) whose internal logic core operates with 0.9 V supply and peripheral circuits operate with 1.8 and 3.3 V supplies. Figure 3. Level shifter generating TXEN and RXEN from OE. The output signals TXEN and RXEN swing from 1.8 to 3.3 V while the input signal OE swings from 0 to 0.9 V.Figure 6. Measured waveforms of the 5.25-V-tolerant bidirectional I/O circuit at the receiver mode. (a) Cascode bias CAS and (b) n-well bias NWB when the signal on the I/O pad toggles between 0 and 5 V at 25 Mbps.

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Section: Introductionmentioning

confidence: 99%

A 5.25‐V‐tolerant bidirectional I/O circuit in a 28‐nm CMOS process

Ahn

Park²,

Yoo

2014

Circuit Theory & Apps

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“…Under this condition, while the required stimulus current is fixed, the output voltage varies correspondingly in a wide range. High operating voltage might result in problems of gate-oxide reliability and hot-carrier effect [16]. In addition, power consumption is also the critical consideration, because it is inversely proportional to the used time of the implantable device.…”

Section: Introductionmentioning

confidence: 99%

Stimulus driver for epilepsy seizure suppression with adaptive loading impedance

Ker¹,

Lin²,

Chen³

2011

J. Neural Eng.

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A stimulus driver circuit for a micro-stimulator used in an implantable device is presented in this paper. For epileptic seizure control, the target of the driver was to output 30 µA stimulus currents when the electrode impedance varied between 20 and 200 kΩ. The driver, which consisted of the output stage, control block and adaptor, was integrated in a single chip. The averaged power consumption of the stimulus driver was 0.24-0.56 mW at 800 Hz stimulation rate. Fabricated in a 0.35 µm 3.3 V/24 V CMOS process and applied to a closed-loop epileptic seizure monitoring and controlling system, the proposed design has been successfully verified in the experimental results of Long-Evans rats with epileptic seizures.

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“…To support high speed interface operation requirements, below 40nm, 1.8V I/O device is usually adopted. For the legacy I/O signal interfaces higher than 2V, it is usually implemented by stacking 1.8V I/O transistors [1], [2] to prevent from introducing 2 nd thicker I/O devices to save the cost. To design an effective ESD power clamp for these higher voltage I/O interface using lower voltage transistors become an important issue in chip design.…”

Section: Introductionmentioning

confidence: 99%

Gate-driven 3.3V ESD clamp using 1.8V transistors

Wang

Chen

Huang

et al. 2011

2011 IEEE International Conference on IC Design &Amp; Technology

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A new gate driven 3.3V ESD clamp circuit using 1.8V transistor is proposed. This new clamp circuit is suitable for ESD protection of legacy 3.3V I/O interface circuit in SOC chips which use only 1.8V I/O transistors. This clamp along with 3.3V I/O have been demonstrated in 40nm 1.8V process. Life-time test can pass 1000-hours prolonged operation. ESD/Latch-up can pass HBM 3KV, MM 300V, and +/-200mA current triggering and 4.95V (1.5 x VDD) over-voltage test. Index Terms-gate-driven, gate oxide over-stress, human-body model (HBM), machine model (MM)

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Design of 2xVDD-tolerant mixed-voltage I/O buffer against gate-oxide reliability and hot-carrier degradation

Cited by 3 publications

References 25 publications

A 5.25‐V‐tolerant bidirectional I/O circuit in a 28‐nm CMOS process

A 5.25‐V‐tolerant bidirectional I/O circuit in a 28‐nm CMOS process

Stimulus driver for epilepsy seizure suppression with adaptive loading impedance

Gate-driven 3.3V ESD clamp using 1.8V transistors

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