Circuit design techniques for low-voltage operating and/or giga-scale DRAMs

Yamagata, T.; Tomishima, Shigeki; Tsukude, M.; Hashizume, Y.; Arimoto, Kazutami

doi:10.1109/isscc.1995.535542

Cited by 23 publications

(9 citation statements)

References 5 publications

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“…A feedback-type level conversion circuit is presented in [17]. This converter requires additional low-threshold-voltage Manuscript (low-) high-voltage transistors, and thus it is not a cost-attractive solution.…”

Section: Introductionmentioning

confidence: 99%

A Stress-Relaxed Negative Voltage-Level Converter

Tsiatouhas

2007

IEEE Trans. Circuits Syst. II

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In this brief, a new embedded negative voltage-level converter (level shifter) is presented. The proposed circuit can convert a positive input signal to a negative output signal with reduced or even without (depending on the application) voltage stress on the used MOS devices. The circuit has been designed in a 0.18-m triple-well standard CMOS technology, using double-gate-oxidethickness MOS transistors with an absolute maximum rating of 4.0 V, a nominal power supply of 1.8 V, and a required negative voltage of 3.3 V. Simulation results are provided to demonstrate the efficiency of the proposed topology. According to the results, 1.82-ns delay and 0.53-mW power consumption are reported. Index Terms-Embedded negative voltage-level converter, level shifter, level conversion, MOS-device voltage stress relaxation.

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Section: Introductionmentioning

confidence: 99%

A Stress-Relaxed Negative Voltage-Level Converter

Tsiatouhas

2007

IEEE Trans. Circuits Syst. II

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“…It is difficult to prevent the noise entirely with the above mentioned solutions. To get longer refresh time characteristics, a boosted sense GND technique (BSG) [l] and a negative word line technique [2] are reported already. Specially a negative word line technique is one of good methods to improve the refresh time characteristics for low voltage operation.…”

Section: System Lsimentioning

confidence: 99%

“…This heat problem has been solved by cooling systems and package technology. (2) The noise induced by large size buffer switching, in particular output buffers connected to large load capacitances degrades the dynamic refresh characteristics of the DRAM drastically. The dynamic refresh characteristics depend on the subthreshold leakage current of the access transistor and correspond to word line and substrate noise.…”

Section: Introductionmentioning

confidence: 99%

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High-speed/high-band width design methodologies for on chip DRAM core multimedia system LSIs

Tsuruda

Kobayashi²,

Tsukude

et al.

Proceedings of Custom Integrated Circuits Conference

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Recently, as multimedia LSIs have developed, the demand for high-speed /high-band width LSIs which integrate the DRAM core and logic elements (CPU etc.) have been strongly required. However, the high-speed / high-band width operation induces the large switching noise. This noise degrades a DRAMS operating margin, and especially the data retention characteristics. In this paper, we analyze the noise transmission model and propose DRAM and logic compatible design methodology maintained the reliability of high-speed /highband width system LSIs. And we obtained good experimental results on the test device. 1.IntroductionIn the DRAM core implemented on system LSIs , there are three main problems as follows:(1) High speed switching in logic sections heats up the die and increases the junction leakage current, degrading the static refresh characteristics of DRAM. This heat problem has been solved by cooling systems and package technology.(2) The noise induced by large size buffer switching, in particular output buffers connected to large load capacitances degrades the dynamic refresh characteristics of the DRAM drastically. The dynamic refresh characteristics depend on the subthreshold leakage current of the access transistor and correspond to word line and substrate noise.(3) As a DRAM requires a boosted potential, the logic section cannot use the optimum transistor for the high speed switching in order to maintain the reliability of the gate oxide film.Here, we focus on the latter two problems and (2) in particular. We examined noise reduction techniques from the view point of circuits and device structures, and propose the best design approach for high-speed /high-band width system LSIs with a DRAM core. W L -0: Junction Leakage BL 0: Subthreshold Leakage 0 0.1 Vth Gate -source voltage Vgs (V) Fig. 1 DRAM cell leakage mechanism 2. The noise analysis for DRAM core implemented on 2.1 Degradation mechanism of dynamic refresh system LSIIn the logic section, a noise which level is lower than the CMOS threshold level is not a severe problem. However, in a DRAM core, noise on the word line increases the subthreshold leakage current of access transistors, exponentially. Fig. 1 shows the leakage mechanism of DRAM cell. If 0.1 V of noise appears on the word line, the leakage current increases ten times and the dynamic refresh time degrades, drastically. Fig. 2 shows the noise level on DRAM array GND level depends on the distance (Dis) between a DRAM core and a switching 20 ns/div. Fig.2 The waveforms of the noise level on DRAM array GND when the buffer is switching. Arrays (a) [Dis=100um] and (b) [Dis=7100uml are shown in Fig.11. 0-7803-3177-6 $5.00 0 1996 IEEE 13.2.1 265 IEEE 1996 CUSTOM INTEGRATED CIRCUITS CONFERENCE

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“…Several circuitry techniques for DRAMs have been developed [1][2][3][4]. Several architectural approaches to reduce DRAM latency have also been developed [5][6][7].…”

Section: Introductionmentioning

confidence: 99%

A dynamic-SDRAM-mode-control scheme for low-power systems with a 32-bit RISC CPU

Miura¹,

Ayukawa²,

Watanabe³

ISLPED'01: Proceedings of the 2001 International Symposium on Low Power Electronics and Design (IEEE Cat. No.01TH8581)

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We have developed a dynamic-SDRAM-mode-control scheme for low-power systems with a 32-bit RISC CPU. The scheme is based on two dynamic changes of SDRAM modes: from active standby to standby and from standby to active standby. It reduces both the operating current and the latency of an SDRAM. An analysis using benchmark programs shows that the developed scheme reduces the SDRAM operating current by 40% and latency by 38% compared to those of standby mode. An SDRAM controller was developed based on this scheme and 0.18-um CMOS technology. The area of the controller is 0.28mm 2 and its operating current is 2.5mA at 1.8V and 100 MHz.

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Circuit design techniques for low-voltage operating and/or giga-scale DRAMs

Cited by 23 publications

References 5 publications

A Stress-Relaxed Negative Voltage-Level Converter

A Stress-Relaxed Negative Voltage-Level Converter

High-speed/high-band width design methodologies for on chip DRAM core multimedia system LSIs

A dynamic-SDRAM-mode-control scheme for low-power systems with a 32-bit RISC CPU

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