Chopper Capacitively Coupled Instrumentation Amplifier Capable of Handling Large Electrode Offset for Biopotential Recordings

Zheng, Jiawei; Ki, Wing-Hung; Hu, Langyu; Tsui, Chi-Ying

doi:10.1109/tcsii.2017.2741348

Cited by 34 publications

(24 citation statements)

References 15 publications

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“…In such a case, a DC-servo loop (DSL) is usually employed to attenuate the electrode offset (EOS) at the output. However, it has to tradeoff between capability of handling EOS and noise [12]. This paper presents a low noise, high input impedance digital-analog hybrid offset suppression amplifier to address the aforementioned challenges.…”

Section: System Overviewmentioning

confidence: 99%

“…Hence a DSL should be added to suppress the EOS and implement a high-pass corner frequency at f L ≈ 0.6 Hz. The high-pass corner frequency is [12]:…”

Section: System Overviewmentioning

confidence: 99%

“…Thus, the input impedance is around 2.5 GΩ at the passband. The input-referred noise of the whole chopper amplifier due to the white noise of the pseudo resistor (P-RES) and G DSL can be estimated as [12]:…”

Section: System Overviewmentioning

confidence: 99%

“…The traditional chopper capacitively coupled instrumentation amplifier with DSL is shown in Figure 4a. According to the analysis in [8,12], the positive feedback loop is rendered inoperative at DC. Therefore, the DC input impedance can be expressed as:…”

Section: Input Impedancementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Low Noise, High Input Impedance Digital-Analog Hybrid Offset Suppression Amplifier for Wearable Dry Electrode ECG Monitoring

Wang

Wei

et al. 2020

Electronics

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The portable real-time electrocardiogram (ECG) is a convenient and promising electronic device for cardiovascular diseases patients. However, unlike wet gel electrodes in traditional clinical applications, dry electrodes are competent for comfortable long-time wearing and can prevent skin ulceration. Its ultra-high source impedance and electrode offset (EOS) make traditional chopper amplifiers with low input impedance and limited EOS range difficult to apply to this area. To overcome these challenges, this paper proposes a novel chopper amplifier topology. This architecture includes a gain control loop, a ripple reduction loop, and a DC-servo loop (DSL). The proposed sampling input stage and digital-analog hybrid DSL are employed to boost input impedance and extend the EOS handing range. Designed with a 0.18 µm 1P6M 1.8 V CMOS salicide process, the proposed chopper capacitively coupled instrumentation amplifier achieves an ultra-high input impedance of 120 GΩ (<0.05 Hz) or 2.1 GΩ (0.6~250 Hz), an EOS handing range of ±325 mV and a low noise of 1.9 μVrms at 0.6~250 Hz. It occupies an area of 0.36 mm2 and only consumes a quiescent current of 11 μA.

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Section: System Overviewmentioning

confidence: 99%

“…Hence a DSL should be added to suppress the EOS and implement a high-pass corner frequency at f L ≈ 0.6 Hz. The high-pass corner frequency is [12]:…”

Section: System Overviewmentioning

confidence: 99%

Section: System Overviewmentioning

confidence: 99%

Section: Input Impedancementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Low Noise, High Input Impedance Digital-Analog Hybrid Offset Suppression Amplifier for Wearable Dry Electrode ECG Monitoring

Wang

Wei

et al. 2020

Electronics

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A fully differential capacitively-coupled high CMRR low-power chopper amplifier for EEG dry electrodes

Shad

Molinas

Ytterdal

2020

Analog Integr Circ Sig Process

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The use of dry electrodes is increasing rapidly. Since their impedance is high, there is a high impedance node at the connecting node between the electrode and amplifier. This leads to absorb powerline signal and high CMRR amplifiers are essential to eliminate this. In this article, we propose a low-power low-noise chopper-stabilized amplifier with high CMRR. In order to minimise the input-referred noise, an inverter-based differential amplifier is utilized. Meanwhile, a DC servo loop is designed to reject the DC offset of the electrode. Since all of the stages required a common-mode feedback, for each of the amplifiers a suitable circuit was used. Furthermore, a chopping spike filter is implemented at the final stage to attenuate the choppers’ spike. Finally, to eliminate the offset effect from the mismatch and post-layout, a DC offset rejection technique is used. The designed circuit is simulated in a standard 180 nm CMOS technology. The designed chopper amplifier consumes just 1.1 $$\upmu \hbox {W}$$μW at a 1.2 $$\hbox {V}$$V supply. The mid-band gain is 40 dB while the bandwidth is from 0.5 to 200 Hz. The total input-referred noise is 1 $$\upmu \hbox {V}_{\mathrm{rms}}$$μVrms in its bandwidth. Thus the NEF and PEF of the designed circuit is 2.7 and 9.7, respectively. In order to analyse the performance of the proposed chopper amplifier against process and mismatch variation, Monte Carlo simulation is done. According to 200 Monte Carlo simulations, CMRR and PSRR are 124 dB with 6.9 dB standard deviation and 107 dB with 7.7 standard deviation, respectively. Ultimately, the total area consumption is 0.1 $$\hbox {mm}^2$$mm2 without pads.

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Miniaturization for wearable EEG systems: recording hardware and data processing

2022

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As more people desire at-home diagnosis and treatment for their health improvement, healthcare devices have become more wearable, comfortable, and easy to use. In that sense, the miniaturization of electroencephalography (EEG) systems is a major challenge for developing daily-life healthcare devices. Recently, because of the intertwined relationship between EEG recording and processing, co-research of EEG recording hardware and data processing has been emphasized for whole-in-one miniaturized EEG systems. This paper introduces miniaturization techniques in analog-front-end hardware and processing algorithms for such EEG systems. To miniaturize EEG recording hardware, various types of compact electrodes and mm-sized integrated circuits (IC) techniques including artifact rejection are studied to record accurate EEG signals in a much smaller manner. Active electrode and in-ear EEG technologies are also researched to make small-form-factor EEG measurement structures. Furthermore, miniaturization techniques for EEG processing are discussed including channel selection techniques that reduce the number of required electrode channel and hardware implementation of processing algorithms that simplify the EEG processing stage.

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Chopper Capacitively Coupled Instrumentation Amplifier Capable of Handling Large Electrode Offset for Biopotential Recordings

Cited by 34 publications

References 15 publications

Low Noise, High Input Impedance Digital-Analog Hybrid Offset Suppression Amplifier for Wearable Dry Electrode ECG Monitoring

Low Noise, High Input Impedance Digital-Analog Hybrid Offset Suppression Amplifier for Wearable Dry Electrode ECG Monitoring

A fully differential capacitively-coupled high CMRR low-power chopper amplifier for EEG dry electrodes

Miniaturization for wearable EEG systems: recording hardware and data processing

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