Dry electrodes are a promising solution for prolonged EEG signal acquisition, whereas wet electrodes may lose their signal quality in the same situation and require skin preparation for setup. Here, we review the impedance and noise of passive and active dry EEG electrodes. In addition, we compare noise and input impedance of the EEG amplifiers. As there are multiple definitions of impedance in each EEG system, they are all first defined. Electrodes must be compatible with amplifiers to accurately record EEG signals. This implies that their impedance plays a significant role in amplifier compatibility and affects total input-referred noise. Therefore, we review the impedance and noise of state-of-the-art amplifiers and electrodes. Furthermore, we compare the various structures and materials used and their final impedance to that of wet electrodes. Finally, we compare state-of-the-art electrodes and amplifiers to the standards of the IFCN and IEC80601-2-26. We investigate bottlenecks and propose a guideline for future work on passive and active dry electrodes, as well as EEG amplifiers.
In this paper, a power efficient, low-noise and high swing capacitively-coupled amplifier (CCA) for neural recording applications is proposed. The use of current splitting technique and current scaling technique in a current mirror operational transconductance amplifier (CM-OTA) has lead to a very good trade-off between power and noise. The presented architecture is simple, without cascode transistor while it has more than 80 dB open-loop gain without extra power consumption. As a result, the proposed strucuture has a better power efficiency factor (PEF) and output swing in comparison with previous reported architectures is increased to the 2Vov below the maximum supply voltage. In order to reduce flicker noise and achieve better trade-off between the power and noise, PMOS transistors with an optimum size have been utilized which operate in sub-threshold region. The amplifier is designed and simulated in a commercially available 0.18 µm CMOS technology. Monte Carlo simulations for process and mismatch have been carried out. The gain of the proposed amplifier is 39.22 dB in its bandwidth (3 Hz-5 kHz). Total input-referred noise is 3.03 µVrms over 1 Hz-10 kHz. The power consumption of the amplifier is 2.98 µW at supply voltage of 1.4 V. The noise efficiency factor (NEF) and PEF are 2.4 and 8.06, respectively. The output swing is about 1.16 V. It means the proposed amplifier can tolerate up to 13.2 mV peakto-peak input signal while its total harmonic distortion (THD) is less than 1%.
Although current-reuse amplifier has been widely used in biomedical applications because of their low inputreferred thermal noise, they don't have high output swing and their gain is limited. In this article, a rail-to-rail current-reuse amplifier with a 92 dB open-loop gain is introduced while its power and noise increment is just 7%. The proposed structure is a two stage amplifier which doesn't need further compensation since all nodes are diode connected except for the output node. In order to show the merit of the proposed structure, the NEF, PEF and SEF of the proposed amplifier in a capacitively-coupled neural amplifier structure is compared to the state-of-the-art neural amplifiers. The amplifier is designed and simulated in a commercially available 0.18 µm CMOS technology. The midband gain of the neural amplifier is 40 dB in the bandwidth between 0.6 Hz and 5 kHz. The proposed structure consumes 1.07 µA current from a 1.2 V supply voltage. The NEF, PEF and SEF of proposed structure are 1.68, 3.4, 0.05, respectively. The total area consumption of the neural amplifier is 0.03 mm 2 without pads.Index Terms-High-swing amplifier, low SEF, current-reuse OTA, high gain, dynamic range * The first two athurs contributed equally.
In this article, a capacitively-coupled neural amplifier based on a new high gain low-noise amplifier is proposed. By utilizing a cross-coupled structure, the open-loop gain of the amplifier is boosted. This modification leads to higher closed-loop gain of the amplifier only with one-stage and reduces the gain error. Besides, the input impedance of the amplifier is boosted by a factor of 100 at 100 Hz using a power-efficient technique.A detail analysis to model the high frequency behaviour of input impedance boosting technique is carried out to show and formulate a limitation. The amplifier is designed and simulated in a commercially available 0.18 µm CMOS technology. The Bandwidth of the amplifier is from 0.5 to 10 kHz and the midband gain is 52 dB. The total input-referred noise is 3.26 µVrms in the bandwidth. The noise and power efficiency factor of proposed amplifier is 1.4 and 1.7 , respectively. The superior performance of the amplifier is achieved by increasing the input capacitor value and exploiting noise efficient amplifier. Furthermore, to show the robustness of the proposed structure, a Monte Carlo simulation is carried out for process variation and mismatch. The mean value of the input impedance and CMRR are 10.5 GΩ and 90 dB, respectively. Finally, the total area consumption without pads is 0.03 mm 2 .
The use of dry electrodes is increasing rapidly. Since their impedance is high, there is a high impedance node at the connecting node between the electrode and amplifier. This leads to absorb powerline signal and high CMRR amplifiers are essential to eliminate this. In this article, we propose a low-power low-noise chopper-stabilized amplifier with high CMRR. In order to minimise the input-referred noise, an inverter-based differential amplifier is utilized. Meanwhile, a DC servo loop is designed to reject the DC offset of the electrode. Since all of the stages required a common-mode feedback, for each of the amplifiers a suitable circuit was used. Furthermore, a chopping spike filter is implemented at the final stage to attenuate the choppers’ spike. Finally, to eliminate the offset effect from the mismatch and post-layout, a DC offset rejection technique is used. The designed circuit is simulated in a standard 180 nm CMOS technology. The designed chopper amplifier consumes just 1.1 $$\upmu \hbox {W}$$μW at a 1.2 $$\hbox {V}$$V supply. The mid-band gain is 40 dB while the bandwidth is from 0.5 to 200 Hz. The total input-referred noise is 1 $$\upmu \hbox {V}_{\mathrm{rms}}$$μVrms in its bandwidth. Thus the NEF and PEF of the designed circuit is 2.7 and 9.7, respectively. In order to analyse the performance of the proposed chopper amplifier against process and mismatch variation, Monte Carlo simulation is done. According to 200 Monte Carlo simulations, CMRR and PSRR are 124 dB with 6.9 dB standard deviation and 107 dB with 7.7 standard deviation, respectively. Ultimately, the total area consumption is 0.1 $$\hbox {mm}^2$$mm2 without pads.
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