CHIPPER: A low-complexity bufferless deflection router

Abstract

As Chip Multiprocessors (CMPs) scale to tens or hundreds of nodes, the interconnect becomes a significant factor in cost, energy consumption and performance. Recent work has explored many design tradeoffs for networks-on-chip (NoCs) with novel router architectures to reduce hardware cost. In particular, recent work proposes bufferless deflection routing to eliminate router buffers. The high cost of buffers makes this choice potentially appealing, especially for lowto-medium network loads.However, current bufferless designs usually add complexity to control logic. Deflection routing introduces a sequential dependence in port allocation, yielding a slow critical path. Explicit mechanisms are required for livelock freedom due to the non-minimal nature of deflection. Finally, deflection routing can fragment packets, and the reassembly buffers require large worst-case sizing to avoid deadlock, due to the lack of network backpressure. The complexity that arises out of these three problems has discouraged practical adoption of bufferless routing.To counter this, we propose CHIPPER (Cheap-Interconnect Partially Permuting Router), a simplified router microarchitecture that eliminates in-router buffers and the crossbar. We introduce three key insights: first, that deflection routing port allocation maps naturally to a permutation network within the router; second, that livelock freedom requires only an implicit token-passing scheme, eliminating expensive age-based priorities; and finally, that flow control can provide correctness in the absence of network backpressure, avoiding deadlock and allowing cache miss buffers (MSHRs) to be used as reassembly buffers. Using multiprogrammed SPEC CPU2006, server, and desktop application workloads and SPLASH-2 multithreaded workloads, we achieve an average 54.9% network power reduction for 13.6% average performance degradation (multiprogrammed) and 73.4% power reduction for 1.9% slowdown (multithreaded), with minimal degradation and large power savings at low-to-medium load. Finally, we show 36.2% router area reduction relative to buffered routing, with comparable timing.

A 1-Cycle 1.25GHz Bufferless Router for 3D Network-on-Chip

“…Bufferless router, which provides a low-cost solution for NoC, has become a hot research issue [2], [3]. However, the serialized switch allocator which lies on the critical path degrades the performance of the traditional bufferless router [4]. A low-complexity bufferless router (called CHIPPER) has been proposed in [4] for 2D mesh NoC.…”

“…However, the serialized switch allocator which lies on the critical path degrades the performance of the traditional bufferless router [4]. A low-complexity bufferless router (called CHIPPER) has been proposed in [4] for 2D mesh NoC. A partial permutation network is used to replace the switch allocator and crossbar in the router.…”

Tree-Mesh Heterogeneous Topology for Low-Latency NoC

“…DyXY [15] is an adaptive routing algorithm designed for meshes, and adaptive XYZ [16] is another adaptive routing for 3D NoCs. Use of deflection routing [10,17] is also proposed to reduce energy consumption at the expense of a small performance loss.…”

Cbufferless: A Novel Congestion Control for Bufferless Networks On-Chip

“…As an alternative design, NoC without buffers (known as bufferless NoC) has been proposed in order to gain more efficiency [7,22]. In bufferless NoC, router buffer is completely eliminated.…”