Chiplet actuary

Feng, Yinxiao; Ma, Kaisheng

doi:10.1145/3489517.3530428

Cited by 23 publications

(10 citation statements)

References 4 publications

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“…However, the size of transistors in IC has now met its physical limit and cannot be reduced as in the past [13]. Therefore, advanced package techniques like interposer-based 2.5D packages are proposed to address this issue to build large-scale systems [14]. Compared to a large monolithic SoC chip, the 2.5D package contains many smaller chiplets, which are partitioned from the monolithic SoC.…”

Section: Preliminaries a Chiplet And Cost Modelmentioning

confidence: 99%

“…where Y is the yield, s is the die area, d 0 is the defect density and α is the cluster parameter. In the 7-nm technology, the typical value of d 0 is 0.09 cm −2 , and the typical value of α is 10 [14]. With this equation, we can estimate the manufacturing costs based on the processed wafer's yield Y and unit price P 0 .…”

Section: Preliminaries a Chiplet And Cost Modelmentioning

confidence: 99%

“…where Y pack , Y chip , Y bond are respectively the yield of the package, the yield of chiplets, and the yield of the bond. The values of each term in our cost model are validated based on data from public information and in-house sources [14].…”

Section: Preliminaries a Chiplet And Cost Modelmentioning

confidence: 99%

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Scene-aware Learning Network for Radar Object Detection

Zheng

Yue

Keutzer

et al. 2021

Proceedings of the 2021 International Conference on Multimedia Retrieval

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Object detection is essential to safe autonomous or assisted driving. Previous works usually utilize RGB images or LiDAR point clouds to identify and localize multiple objects in self-driving. However, cameras tend to fail in bad driving conditions, e.g. bad weather or weak lighting, while LiDAR scanners are too expensive to get widely deployed in commercial applications. Radar has been drawing more and more attention due to its robustness and low cost. In this paper, we propose a scene-aware radar learning framework for accurate and robust object detection. First, the learning framework contains branches conditioning on the scene category of the radar sequence; with each branch optimized for a specific type of scene. Second, three different 3D autoencoder-based architectures are proposed for radar object detection and ensemble learning is performed over the different architectures to further boost the final performance. Third, we propose novel scene-aware sequence mix augmentation (SceneMix) and scene-specific post-processing to generate more robust detection results. In the ROD2021 Challenge, we achieved a final result of average precision of 75.0% and an average recall of 81.0%. Moreover, in the parking lot scene, our framework ranks first with an average precision of 97.8% and an average recall of 98.6%, which demonstrates the effectiveness of our framework. CCS CONCEPTS• Computing methodologies → Object detection; Scene understanding; Neural networks.

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Section: Preliminaries a Chiplet And Cost Modelmentioning

confidence: 99%

Section: Preliminaries a Chiplet And Cost Modelmentioning

confidence: 99%

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Scene-aware Learning Network for Radar Object Detection

Zheng

Yue

Keutzer

et al. 2021

Proceedings of the 2021 International Conference on Multimedia Retrieval

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“…Chiplet technology has emerged as a promising solution to this challenge, allowing multiple specialized chips to be integrated into a more extensive system. [1][2][3][4][5] This approach offers cost reduction, improved yield, shorter design cycles, and better integration. The die-to-die short-reach wireline communication link with high pin/energy efficiency is critical for chiplet technology, which can be applied to memory interconnects and electrical/optical (E/O) interfaces.…”

Section: Introductionmentioning

confidence: 99%

“…As the integrated‐circuit feature sizes approach the physical limit, the cost of realizing high‐performance system‐on‐chip (SOC) increases significantly. Chiplet technology has emerged as a promising solution to this challenge, allowing multiple specialized chips to be integrated into a more extensive system 1–5 . This approach offers cost reduction, improved yield, shorter design cycles, and better integration.…”

Section: Introductionmentioning

confidence: 99%

A 25‐Gb/s/pin ground‐referenced signaling transceiver with a DC‐coupled equalizer for on‐package communication

Guo,

Chen,

Wang

et al. 2023

Circuit Theory & Apps

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SummaryThis paper proposes a wireline serial link transceiver for on‐package die‐to‐die links based on 12‐nm fin field‐effect transistor (FinFET) technology. The link is crucial for improving the computational performance of larger systems built from chiplets. To achieve high pin/energy efficiency and prevent traditional single‐ended signaling disadvantages, the transceiver adopts single‐ended ground‐reference signaling (GRS) to transfer information. To precompensate for the frequency‐dependent loss, retain the advantages of GRS, and avoid the disadvantages of traditional AC‐coupled equalizer, the transmitter in the transceiver adopts a DC‐coupled switched‐capacitor charge pump equalizer that can transmit GRS and its equilibrium value can be adjusted according to the channel attenuation. This paper proposes a method for timing de‐skew using digital control delay lines to eliminate the timing skew between data and the clock. In addition, this paper presents a duty cycle corrector to avoid duty cycle distortion, with an adjustment range of 44.5% to 52% and a power dissipation of only 30 W. The transceiver has an area of 1.016 0.676 mm2, including one clock lane link and four data lane links. At a nominal 0.8‐V power supply voltage, the aggregate eye‐opening of the measured 25 Gb/s data on an organic substrate channel with an attenuation of −2.2 dB over 6 mm is 0.675 UI, with a bit error rate (BER) of less than 10−12 and an energy efficiency of 1.01 pJ/bit.

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