Chip to wafer direct bonding technologies for high density 3D integration

Sanchez, L.; Bally, Laurent; Montmayeul, Brigitte; Fournel, Frank; DaFonseca, J.; Augendre, E.; Cioccio, L. Di; Carron, V.; Signamarcheix, T.; Taibi, R.; Mermoz, S.; Lecarpentier, Gilbert

doi:10.1109/ectc.2012.6249108

Cited by 28 publications

(9 citation statements)

References 5 publications

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“…A specific holder compatible with the SET's FC300 flip-chip bonder has been developed for this purpose. The alignment accuracy is less than one micrometer [1].…”

Section: Copper Direct Bonding Processingmentioning

confidence: 99%

Towards alternative technologies for fine pitch interconnects

Colonna

Segaud

Marion

et al. 2013

2013 IEEE 63rd Electronic Components and Technology Conference

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This study focuses on alternative technologies for fine pitch 3D interconnect. These technologies are: µ-inserts (insertion of a nickel cylinder in Aluminium pad), µ-tubes (insertion of a hard tube in Aluminium pad), Transient Liquid Phase (TLP) bonding (whole solder reacts to form intermetallic compound) and copper direct bonding. In the first part the process flow is described. Then electrical performances are presented, including a comparison of the Kelvin resistance for each technology. The next part presents reliability considerations, where the failure modes and the weaknesses of each interconnect technologies are described. The mechanical impact of insertion technologies is also studied. IntroductionOne of the most promising features of 3D Integration is the large communication bandwidth between chips. This can only be achieved through high density TSVs and interconnects. In face to back (F2B) stacking, the interconnect pitch is limited by TSV, but in face to face (F2F) stacking, there is no such limitation. Aggressive pitch is therefore one the top requirement for 3D interconnects. In this study, we will assess and compare different 3D interconnect technologies for sub-20µm pitch. These technologies are: µ-inserts (insertion of a nickel cylinder in Aluminium pad), µ-tubes (insertion of a hard tube in Aluminium pad), Transient Liquid Phase (TLP) bonding (whole solder reacts to form intermetallic compound) and Copper direct bonding. These interconnects have been developed for different application domains, with process temperatures ranging from room temperature to 400°C. In the first part the process flow and the assembly technology used for each type of interconnect are described. The second part focuses on electrical performances. The classical solder bonding technology using µ-bump is also presented as a reference. The Kelvin resistance is used to compare the electrical performance of each interconnect technology. In the last part, reliability considerations are presented. The failure modes and the weaknesses of each interconnect technologies are described. The mechanical impact of insertion technologies is also studied with finite element modeling.

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“…A specific holder compatible with the SET's FC300 flip-chip bonder has been developed for this purpose. The alignment accuracy is less than one micrometer [1].…”

Section: Copper Direct Bonding Processingmentioning

confidence: 99%

Towards alternative technologies for fine pitch interconnects

Colonna

Segaud

Marion

et al. 2013

2013 IEEE 63rd Electronic Components and Technology Conference

View full text Add to dashboard Cite

show abstract

“…The more matured integration method is transfer bonding and consists of preparing millimeter-size InP dies bonded on localized regions of a patterned and planarized SOI wafers (Figure 9). A faster and more efficient method than pick-and-place is to do a collective transfer of III-V dies using a die holder [157][158] . The technique consists of positioning the dies on an adapted surface and proceeding with the wafer bonding in a single step ( Figure 10).…”

Section: Iii-v Materials Integration On Simentioning

confidence: 99%

Building blocks of silicon photonics

Vivien

Baudot

Bœuf

et al. 2019

Future Directions in Silicon Photonics

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“…Because of this, the following applications are likely to be among the early adopters of these micro-LED displays. The first are micro-display applications for AR/MR (Augmented-/Mixed-Reality), where the silicon CMOS backplane IC and LEDs are hybridized by wafer-to-wafer bonding [2]. The second are super-size display applications, such as outdoor signage or TV screens larger than 110 inch,…”

Section: Introductionmentioning

confidence: 99%

CMOS Backplane Pixel Circuit With Leakage and Voltage Drop Compensation for an Micro-LED Display Achieving 5000 PPI or Higher

et al. 2020

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Micro-displays based on micro-LEDs are becoming more and more attractive in AR/MR (Augmented/Mixed Reality) applications. A display size of 0.5 to 0.7-inch is preferred, with 5,000 PPI (Pixel Per Inch) or higher. Due to this pixel density and size, a CMOS (Complementary Metal-Oxide-Silicon) backplane is an ideal solution to drive these pixelized micro-LEDs. As the required pixel size gets smaller, the design of the appropriate pixel circuit becomes more challenging. The simplest 2T1C (2 transistors & 1 capacitor) pixel circuit has potential problems, due to the leakage current of the switch transistor and the voltage drop on the matrix array layout. In this paper, a pixel circuit is proposed as a solution to overcome these two issues. Our simulation results show that the variation of the driving current to the LED is improved by 95 %, and the IR drop error rate is around 2.2 % compared to the 2T1C circuit. The test results also show that the error rate of I PIXEL for the whole region of display is under 2.5 %. This work is verified using a test chip implementation with 180 nm CMOS process technology. INDEX TERMS Micro-LED display, microdisplay, high-resolution, DRAM type, voltage driving, low leakage switch, IR drop compensation, CMOS backplane, and high-PPI.

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Chip to wafer direct bonding technologies for high density 3D integration

Cited by 28 publications

References 5 publications

Towards alternative technologies for fine pitch interconnects

Towards alternative technologies for fine pitch interconnects

Building blocks of silicon photonics

CMOS Backplane Pixel Circuit With Leakage and Voltage Drop Compensation for an Micro-LED Display Achieving 5000 PPI or Higher

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