Chip-to-wafer (C2W) 3D integration with well-controlled template alignment and wafer-level bonding

Chen, Qianwen; Zhang, Dingyou; Wang, Zheyao; Liu, Litian; Lu, James

doi:10.1109/ectc.2011.5898482

Cited by 23 publications

(16 citation statements)

References 15 publications

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“…To avoid the drawbacks of the pick-align-bond step for each die and thermal accumulation in C2W, novel alignment methods using self-assembly [184]- [188] and templates [189], [190] have been developed as alternatives to conventional optical alignment. Both of these methods first reconfigure multiple individual chips into a single wafer configuration using simultaneous alignment, and then bond the entire reconfigured wafer in a single bonding step.…”

Section: ) Emerging Materials and Methodsmentioning

confidence: 99%

3-D Integration and Through-Silicon Vias in MEMS and Microsensors

Wang

2015

J. Microelectromech. Syst.

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After two decades of intensive development, 3-D integration has proven invaluable for allowing integrated circuits to adhere to Moore's Law without needing to continuously shrink feature sizes. The 3-D integration is also an enabling technology for hetero-integration of microelectromechanical systems (MEMS)/microsensors with different technologies, such as CMOS and optoelectronics. This 3-D heterointegration allows for the development of highly integrated multifunctional microsystems with small footprints, low cost, and high performance demanded by emerging applications. This paper reviews the following aspects of the MEMS/ microsensor-centered 3-D integration: fabrication technologies and processes, processing considerations and strategies for 3-D integration, integrated device configurations and wafer-level packaging, and applications and commercial MEMS/ microsensor products using 3-D integration technologies. Of particular interest throughout this paper is the heterointegration of the MEMS and CMOS technologies. [2015-0158]Index Terms-Three-dimensional (3-D) integration, microelectromechanical systems (MEMS), microsensor, packaging, hetero-integration, interposer, through-silicon-via (TSV), waferlevel packaging, microsystem.

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Section: ) Emerging Materials and Methodsmentioning

confidence: 99%

3-D Integration and Through-Silicon Vias in MEMS and Microsensors

Wang

2015

J. Microelectromech. Syst.

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“…A similar C2W alignment approach was proposed with a patterned BCB layer as the alignment template [24]. Such template alignment techniques eliminate the requirement of C2W bonding tools [25], and they promise comparable alignment accuracy by manual die insertion into the cavity.…”

Section: A Chip Embeddingmentioning

confidence: 99%

Post-CMOS Processing and 3-D Integration Based on Dry-Film Lithography

Temiz

Guiducci

Leblebici

2013

IEEE Trans. Compon., Packag. Manufact. Technol.

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Abstract-This paper presents a chip-level postcomplementary metal oxide semiconductor (CMOS) processing technique for 3-D integration and through-silicon-via (TSV) fabrication. The proposed technique is based on dry-film lithography, which is a low-cost and simple alternative to spincoated resist. Unlike conventional photolithography methods, the technique allows resist patterning on very high topography, and therefore chip-level photolithography can be done without using any wafer reconstitution approach. Moreover, this paper proposes a via sidewall passivation method which eliminates dielectric etching at the bottom of the via and simplifies the whole integration process. In this paper, two 50-μm-thick chips were post-processed, aligned, bonded, and connected by Cu TSVs, which have parylene sidewall passivation. Daisy-chain resistance measurements show 0.5-resistance on average for 60-μm-diameter TSVs, with a yield of more than 99% for 1280 TSVs from five different chip stacks. Subsequently, the techniques were applied to CMOS microprocessor stacking as a test vehicle. Die-level post-CMOS processing for 40-μm-diameter via etching, redistribution layer patterning, and chip-to-chip bonding were successfully demonstrated with the real chips.Index Terms-3-D integration, die-level processing, dry-film lithography, parylene bonding, post-complementary metal oxide semiconductor (CMOS) processing, through-silicon via (TSV), via-last TSV.

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“…In recent years, 3D integration technology has been widely explored with different approaches [1]- [2], and has been applied to various ICs such as memory [3], image sensor [4], and micro-processor [5].…”

Section: Introductionmentioning

confidence: 99%

Development of ultra-low capacitance through-silicon-vias (TSVs) with air-gap liner

Chen

Huang

Wang

2013

2013 IEEE 63rd Electronic Components and Technology Conference

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This paper presents the development of ultra-low capacitance TSVs using air-gap to replace conventional SiO 2 as the insulating liners. Two polymer sacrificial technologies, including Benzocyclobutene (BCB) etching and Propylene Carbonate (PPC) pyrolysis, have been developed to successfully realize the air-gap TSVs. The capacitance-voltage (C-V) characteristics and the leakage current have been measured to evaluate the electrical performances of the air-gap TSVs, and the thermal-mechanical stress has been studies with ANSYS. The measurement results show that the air-gap TSVs have a capacitance density around 0.6 nF/cm 2 at the maximum depletion region, and the leakage current is less than 110 -12 A at 20 V biased voltage, indicating that air-gaps are able to achieve low capacitance and good insulating property. The simulation results show that the air-gap is effective to reduce the thermal stresses in the silicon substrate, which is beneficial for devices performance.

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Chip-to-wafer (C2W) 3D integration with well-controlled template alignment and wafer-level bonding

Cited by 23 publications

References 15 publications

3-D Integration and Through-Silicon Vias in MEMS and Microsensors

3-D Integration and Through-Silicon Vias in MEMS and Microsensors

Post-CMOS Processing and 3-D Integration Based on Dry-Film Lithography

Development of ultra-low capacitance through-silicon-vias (TSVs) with air-gap liner

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