Chip-set for video display of multimedia information

Jaspers, E.G.T.

doi:10.1109/30.793577

Cited by 40 publications

(10 citation statements)

References 5 publications

(3 reference statements)

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“…We used three different benchmarks in our experiments: Multi-window Display (MWD) [10], and two MPEG-4 decoders, Core Profile Level 1 (CPL1) and Core Profile Level 2 (CPL2) [11]. We determined application computation and storage needs (and thus critical quantities of slack) using profiling.…”

Section: A Applications and Architecturesmentioning

confidence: 99%

Cost-effective slack allocation for lifetime improvement in NoC-based MPSoCs

Meyer¹,

Hartman²,

Thomas³

2010

2010 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE 2010)

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Wear-out related permanent faults are projected to make system lifetime a critical issue for all designs. In embedded systems, lifetime can be increased using slack, underutilization in execution and storage resources, so that when components fail, data and tasks can be re-mapped and re-scheduled. The design space of possible slack allocation is both large and complex. However, based on the observation that useful slack is often quantized, we have developed an approach that effectively and efficiently allocates execution and storage slack to jointly optimize system lifetime and cost. While exploring less than 1.4% of the slack allocation design space, our approach consistently outperforms alternative slack allocation techniques to find sets of designs within 1.4% of the lifetime-cost Pareto-optimal front.

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Section: A Applications and Architecturesmentioning

confidence: 99%

Cost-effective slack allocation for lifetime improvement in NoC-based MPSoCs

Meyer¹,

Hartman²,

Thomas³

2010

2010 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE 2010)

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“…These frames include 1 I-frame and 40 P-frames. We also perform the evaluation by choosing two application cases: Video Object Plane Decoder (VOPD) and Multi-Window Displayer (MWD), presented in [10,6], to show the resource improvement for the custom NoC. The two evaluation metrics are "power" and "performance".…”

Section: Experimental Evaluationmentioning

confidence: 99%

A low-power crossroad switch architecture and its core placement for network-on-chip

Chang

Shen

Chen

2005

Proceedings of the 2005 International Symposium on Low Power Electronics and Design - ISLPED '05

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As the number of cores on a chip increases, power consumed by the communication structures takes significant portion of the overall power-budget. The individual components of the SoCs will be heterogeneous in nature with widely varying functionality and communication requirements. The communication topology should possibly match communication workflows among these components. In this paper, we first propose an interconnection architecture for SoC, which uses crossroad switches to construct a dedicated communication path dynamically between any two cores. We then present a design methodology for constructing network on chip (NoC) for application-specific computer systems with profiled communication characteristics. We design a core placement tool, which automatically maps cores to a communication topology such that we can minimize the total communication energy. Experimental results show that the design methodology can generate optimized on-chip networks with fewer resources than meshes and tori, and the power saving approximates to 40%.

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“…A MIMO-OFDM receiver in which some of the IPs have been parallelized to multiple IPs (Yoon et al, 2006). A Picture-In-Picture application (PIP) and a Multi-Window Display application (MWD) (Jaspers and De With, 1999;Van Der Tol and Jaspers, 2002). The set of applications have been mapped into an 8x8 mesh topology using the mapping technique proposed in (Tornero et al, 2009).…”

Section: Case Studymentioning

confidence: 99%

“…For instance, the communication flows involved in MMS-Enc and MMS-Dec use a packet size tuned on the basis of a macroblock. Packet injection rate has been computed for each communication flow on the basis of the bandwidth requirements for each application as reported in (Hu and Marculescu, 2005;Yoon et al, 2006;Jaspers and De With, 1999;Van Der Tol and Jaspers, 2002). Table 1 reports the percentage reduction of total energy consumption, energy per flit and average power dissipation of OE-PWR and OE-PWR-DEn as respect to XY.…”

Section: Case Studymentioning

confidence: 99%

Coupling Routing Algorithm and Data Encoding for Low Power Networks on Chip

Palesi

Patti²,

Ascia³

et al. 2015

Journal of Computer Science

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Abstract:The routing algorithm used in a Network-on-Chip (NoC) has a strong impact on both the functional and non functional indices of the overall system. Traditionally, routing algorithms have been designed considering performance and cost as the main objectives. In this study we focus on two important non functional metrics, namely, power dissipation and energy consumption. We propose a selection policy that can be coupled with any multi-path routing function and whose primary goal is reducing power dissipation. As technology shrinks, the power dissipated by the network links represents an ever more significant fraction of the total power budget. Based on this, the proposed selection policy tries to reduce link power dissipation by selecting the output port of the router which minimises the switching activity of the output link. A set of experiments carried out on both synthetic and real traffic scenarios is presented. When the proposed selection policy is used in conjunction with a data encoding technique, on average, 31% of energy reduction and 37% of power saving is observed. An architectural implementation of the selection policy is also presented and its impact on cost (silicon area) and power dissipation of the baseline router is discussed.

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Chip-set for video display of multimedia information

Cited by 40 publications

References 5 publications

Cost-effective slack allocation for lifetime improvement in NoC-based MPSoCs

Cost-effective slack allocation for lifetime improvement in NoC-based MPSoCs

A low-power crossroad switch architecture and its core placement for network-on-chip

Coupling Routing Algorithm and Data Encoding for Low Power Networks on Chip

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