A low-power crossroad switch architecture and its core placement for network-on-chip

Chang, Kuei-Chung; Shen, Jih-Sheng; Chen, Tien-Fu

doi:10.1145/1077603.1077693

Cited by 13 publications

(7 citation statements)

References 13 publications

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“…However, it is very likely that the probe message is blocked by currently established circuits or other probes, in particular when the network is highly loaded. In this case, the probe can either wait for the resources to become available [13], or tear down the in-use circuits [14]. Alternatively, some more intelligent search algorithms, such as probe backtracking [11] or parallel probing [9] can be used.…”

Section: Circuit Path Computation and Tdm Slot Allocationmentioning

confidence: 99%

Integrated circuit-packet switching NoC with efficient circuit setup mechanism

2014

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Reducing the NoC power is critical for scaling up the number of nodes in future many-core systems. Most NoC designs adopt packet-switching to benefit from its high throughput and excellent scalability. These benefits, however, come at the price of the power consumption and latency overheads of routers. Circuit-switching, on the other hand, enjoys a significant reduction in power and latency of communication by directing data over pre-established circuits, but the relatively large circuit setup time and low resource utilization of this switching mechanism is often prohibitive. In this paper, we address one of the major problems of circuit-switching, i.e. the circuit setup time overhead, by an efficient and fast algorithm based on the time-division multiplexing scheme. We then further improve the performance by reserving circuits for anticipated messages, and hence completely hide circuit setup time. To address the low resource utilization problem, we integrate the proposed circuit-switching into a packet-switched NoC and use unused circuit resources to transfer packet-switched data. Evaluation results show considerable reduction in NoC power consumption and packet latency.

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Section: Circuit Path Computation and Tdm Slot Allocationmentioning

confidence: 99%

Integrated circuit-packet switching NoC with efficient circuit setup mechanism

2014

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“…The router consists of packet process units (ingress and egress), an arbitration unit, and a switch fabric, and it provides a robust data transfer medium for the functional IP modules. Another solution for scalable architectures is to use circuit-switched NoC [6][7][8]. Chang [8] proposed a circuit-switched interconnection architecture which uses crossroad switches to construct dedicated channels dynamically between any pairs of cores for application-specific SoCs with few tens of cores.…”

Section: Related Workmentioning

confidence: 99%

Reliable network-on-chip design for multi-core system-on-chip

Chang

2009

J Supercomput

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Network-on-chip (NoC) architectures must deliver good latency-through put performance in the face of tight power and area budgets. However, in highperformance chip design, a significant design challenge is how to fulfill the requirements of circuit noise elimination, since the faults will slow down performance and dissipate much of the overall system power. This paper presents a simple coding scheme for reducing power dissipation, crosstalk noise, and crosstalk delay on the bus while simultaneously detecting errors at runtime. It uses a simple bus-invert encoding technique to reduce the prohibited transitions in terms of crosstalk noise and power dissipation. We also design a corresponding detector to detect errors at the input of the NoC routers. It can save energy by interrupting communications without storing and routing the packets when errors occur during transmissions. The experimental results for various multimedia applications show significant reduction in the number of patterns that are most likely to produce crosstalk errors. The results also show that it is attractive in terms of cost to apply the detecting logic to routers in the NoC with respect to the power consumption.

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“…Chang et al [4] extend the NoC power consumption model proposed by Hu. In this model the average energy consumption while sending a data bit from point t i to point t j is given by the summation of the energy spent in the routers and communication wires that links these two points through a given route.…”

Section: Introductionmentioning

confidence: 99%

NoC Power Estimation at the RTL Abstraction Level

Guindani

Reinbrecht

Raupp

et al. 2008

2008 IEEE Computer Society Annual Symposium on VLSI

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The increasing use of mobile electronic devices forces the design of integrated circuits to consider low power techniques. Current power estimation models for oCs capitalize mostly in the volume of information transmitted through the network. This work presents a more precise oC power estimation model, based in buffer reception rates, according to the traffic scenario applied to the network. Results show the accuracy of the model compared to industrial power estimation tools, with reduced execution time. The proposed method allows exploring the oC design space, being employed to evaluate the benefit on using the multicast service.

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A low-power crossroad switch architecture and its core placement for network-on-chip

Cited by 13 publications

References 13 publications

Integrated circuit-packet switching NoC with efficient circuit setup mechanism

Integrated circuit-packet switching NoC with efficient circuit setup mechanism

Reliable network-on-chip design for multi-core system-on-chip

NoC Power Estimation at the RTL Abstraction Level

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