Chip Performance Prediction Using Machine Learning Techniques

Su, Min-Yan; Lin, Wenzhi; Kuo, Ying Hwa; Li, Chien-Mo; Fang, Eric Jia-Wei; Hsueh, Sung S.-Y.

doi:10.1109/vlsi-dat52063.2021.9427338

Cited by 5 publications

(2 citation statements)

References 9 publications

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“…ML/AI strategies can be used to address this issue. A low-cost machine learning-based chip performance prediction framework using on-chip resources is proposed [120]. It predicts the maximum operating frequency of chips for speed binning with an accuracy of over 90% w.r.t Automatic Test equipment (ATE).…”

Section: E Post Layout Simulationmentioning

confidence: 99%

AI/ML Algorithms and Applications in VLSI Design and Technology

Amuru¹,

Vudumula²,

K.³

et al. 2022

Preprint

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An evident challenge ahead for the integrated circuit (IC) industry in the nanometer regime is the investigation and development of methods that can reduce the design complexity ensuing from growing process variations and curtail the turnaround time of chip manufacturing. Conventional methodologies employed for such tasks are largely manual; thus, time-consuming and resource-intensive. In contrast, the unique learning strategies of artificial intelligence (AI) provide numerous exciting automated approaches for handling complex and dataintensive tasks in very-large-scale integration (VLSI) design and testing. Employing AI and machine learning (ML) algorithms in VLSI design and manufacturing reduces the time and effort for understanding and processing the data within and across different abstraction levels via automated learning algorithms. It, in turn, improves the IC yield and reduces the manufacturing turnaround time. This paper thoroughly reviews the AI/ML automated approaches introduced in the past towards VLSI design and manufacturing. Moreover, we discuss the scope of AI/ML applications in the future at various abstraction levels to revolutionize the field of VLSI design, aiming for high-speed, highly intelligent, and efficient implementations.

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Section: E Post Layout Simulationmentioning

confidence: 99%

AI/ML Algorithms and Applications in VLSI Design and Technology

Amuru¹,

Vudumula²,

K.³

et al. 2022

Preprint

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“…Hence, on-chip sensors, which can measure the delay of the critical paths [ 21 , 22 , 23 , 24 , 25 , 26 ], or monitor the worst slack of critical paths [ 27 , 28 , 29 ], are adopted to infer the speed bins of the chip. A low-overhead solution for characterizing the

of a circuit is proposed in [ 30 ], which chooses a small set of representative paths in a circuit and dynamically configures them into ring oscillators to compute the

.Sensors combined with machine learning [ 31 , 32 , 33 ] and data mining are also applied to the speed binning test. Refs.…”

Section: Introductionmentioning

confidence: 99%

On-Chip Structures for Fmax Binning and Optimization

Zhang¹,

Ren²,

Su³

2022

Sensors

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Process variations during manufacturing lead to differences in the performance of the chips. In order to better utilize the performance of the chips, it is necessary to perform maximum operation frequency (Fmax) tests to place the chips into different speed bins. For most Fmax tests, significant efforts are put in place to reduce test cost and improve binning accuracy; e.g., our conference paper published in ICICM 2017 presents a novel binning sensor for low-cost and accurate speed binning. However, by promoting chips placed at the lower bins, because of conservative binning, into higher bins, the overall profit can greatly increase. Therefore, this paper, extended based on a conference paper, presents a novel and adaptive methodology for speed binning, in which the paths impacting the speed bin of a specific IC are identified and adapted by our proposed on-chip Binning Checker and Binning Adaptor. As a result, some parts at a bin margin can be promoted to higher bins. The proposed methodology can be used to optimize the Fmax yield of a digital circuit when it has redundant timing in clock tree, and it can be integrated into current Fmax tests with low extra cost. The proposed adaptive system has been implemented and validated on five benchmarks from ITC, ISCAS89, and OpenSPARCT2 core on 28 nm Altera FPGAs. Measurement results show that the number of higher bin chips is improved by 7–16%, and our cost analysis shows that the profit increase is between 1.18% and 3.04%.

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