2007
DOI: 10.1093/ietele/e90-c.4.848
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Chip-Level Performance Maximization Using ASIS (Application-Specific Interconnect Structure) Wiring Design Concept for 45 nm CMOS Generation

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“…The performance of large-scale integrated circuits (LSIs) is limited by increasing interconnect capacitance and resistance, with the continuous scaling down of LSI feature size, resulting in large propagation delay time and power dissipation. [1][2][3][4] Concerning interconnect materials, a copper (Cu) interconnect with low resistivity and various kinds of dielectric materials with low dielectric constant (low-k) have been realized. In the scaled-down LSIs of below the 45 nm node, the increasing interconnect resistance and the reliability degradation due to higher current density are the main issues.…”
Section: Introductionmentioning
confidence: 99%
“…The performance of large-scale integrated circuits (LSIs) is limited by increasing interconnect capacitance and resistance, with the continuous scaling down of LSI feature size, resulting in large propagation delay time and power dissipation. [1][2][3][4] Concerning interconnect materials, a copper (Cu) interconnect with low resistivity and various kinds of dielectric materials with low dielectric constant (low-k) have been realized. In the scaled-down LSIs of below the 45 nm node, the increasing interconnect resistance and the reliability degradation due to higher current density are the main issues.…”
Section: Introductionmentioning
confidence: 99%