Chip design for monobit receiver

Abstract

A design for the monobit-receiver applicationspecific integrated circuit (ASIC) will be described. The monobit receiver is a wide-band (1-GHz) digital receiver designed for electronic-warfare applications. The receiver can process two simultaneous signals and has the potential for fabrication on a single multichip module (MCM). The receiver consists of three major elements: a nonlinear RF front end, a signal sampler and formatting system (analog-to-digital converter (ADC) and demultiplexers), and a patented "monobit" algorithm implemented as an ASIC for signal detection and frequency measurement. The receiver's front end, ADC, and algorithm experimental performance results were previously presented [1]. The receiver uses a 2-b ADC operating at 2.5 GHz whose outputs are collected and formatted by demultiplexers for presentation to the ASIC. The ASIC has two basic functions: to perform a fast Fourier transform (FFT) and to determine the number of signals and report their frequencies. The ASIC design contains five stages: the input, the FFT, the initial sort, the squaring and addition, and the final sort. The chip will process the ADC outputs in real time, reporting detected signal frequencies every 102.4 ns.Index Terms-Analog-to-digital converter (ADC), fast Fourier transform (FFT), instantaneous frequency measurement (IFM) receivers.

Design and performance evaluation of a digital wideband receiver on a hybrid computing platform

“…This disparity is the primary impediment in radar receiver design implementation, especially for single processor-based systems. Many practical digital receivers compensate the high sampling rate of ADCs to accommodate the speed at which the detection logic in the processor can +++ process the data [2] [3]. However, for real-time and more efficient operation, signal processors in digital radar receivers of the future will need to process data at a rate commensurate with the sampling speed of ADCs [4].…”

“…However, FFT is always computationally intensive in digital receiver systems and hence the length of FFT was in general limited to 256 [2][3][5] [6]. Several techniques have been proposed to reduce the computational complexity of the FFT operations.…”

Modular Design of High-Throughput, Low-Latency Sorting Units

“…Sorting is an important operation in a wide range of applications including data mining, databases [7,19,31], digital signal processing [47,48], network processing, communication switching systems [4,58], scientific computing [15], searching, scheduling [51], pattern recognition, robotics [10], image and video processing [11,12,17,49], and high-energy physics (HEP) [23,55]. For applications that require very high-speed sorting, hardware sorting units are often implemented using either ASICs or FPGAs to meet performance requirements [13,28,31,33,38,41,49].…”

Implementing FFT-based digital channelized receivers on FPGA platforms

“…This can be accomplished by avoiding complex multiplications: Using a monobit kernel for the FFT [22,23]. This algorithm can be further simplified by reducing the number of bits to represent the input samples.…”