Charge-Trapping Phenomena in HfO<sub>2</sub>-Based FeFET-Type Nonvolatile Memories

Yurchuk, Ekaterina; Müller, Johannes; Müller, Stefan; Paul, J.; Pešić, Milan; Bentum, Ralf van; Schroeder, Uwe; Mikolajick, Thomas

doi:10.1109/ted.2016.2588439

Cited by 243 publications

(119 citation statements)

References 25 publications

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“…On the other hand, due to the depolarization field contributed from the DE layer, there is no negative curvature presented in the free energy profile, and therefore no abrupt switching is observed in I d -V g . Note that in real devices, charging defects at the FE/DE interface or within the DE layer due to a strong electric field may significantly reduce charge boost or memory window established by the FE layer [36]. Consequently, having a proper ratio between FE and DE layers not only makes FeFETs work in the correct mode, but also minimizes the unwanted charging effects.…”

Section: A Steady-state Behavior Of Ferroelectric Field-effecttransimentioning

confidence: 99%

A Thermodynamic Perspective of Negative-Capacitance Field-Effect Transistors

Chang

Avci

Nikonov

et al. 2017

IEEE J. Explor. Solid-State Comput. Devices Circuits

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Physical phenomena underlying operation of ferroelectric field-effect transistors (FeFETs) is treated within a unified simulation framework. The framework incorporates the Landau mean-field treatment of free energy of a ferroelectric and the polarization dynamics according to Landau-Khalatnikov (LK) equation. These equations are self-consistently solved with the one-dimensional metal-oxide-semiconductor (MOS) structure electrostatics and the drift-diffusion solution for the current in the semiconductor channel. Numerical simulations demonstrate, depending on the ferroelectric (FE) thickness, both regimes of hysteresis switching (relevant for a non-volatile memory) and of higher on-currents and steeper subthreshold slope (SS) with a negligible hysteresis (relevant for logic) via the negative capacitance effect.

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Section: A Steady-state Behavior Of Ferroelectric Field-effecttransimentioning

confidence: 99%

A Thermodynamic Perspective of Negative-Capacitance Field-Effect Transistors

Chang

Avci

Nikonov

et al. 2017

IEEE J. Explor. Solid-State Comput. Devices Circuits

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“…It should be noted that the ferroelectric induced memory window is entirely different from the trap‐induced gate hysteresis in a transistor, which are normally in the clockwise direction. [ 45 ] To further confirm the correlation between the memory window and the ferroelectricity, we fabricated control devices with and without undergoing postannealing process at 400 °C (see Supporting Information S5 for more details). As shown in Figure S6 (Supporting Information), the transfer curve without postannealing shows nearly no hysteresis, indicating that HZO without postannealing could serve as the paraelectric dielectric layer since the trap‐induced hysteresis is negligible.…”

Section: Resultsmentioning

confidence: 99%

A van der Waals Synaptic Transistor Based on Ferroelectric Hf_0.5Zr_0.5O₂ and 2D Tungsten Disulfide

Chen

Wang

Peng

et al. 2020

Adv Elect Materials

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Neuromorphic computing on the hardware level is promising for performing ever‐increasing data‐centric tasks owing to its superiority to conventional von Neumann architecture in terms of energy efficiency and learning ability. One key aspect to its implementation is the development of artificial synapses that can effectively emulate the multiple functionalities exhibited by their biological counterparts. Here, building on an inorganic ferroelectric gate stack integrated with a 2D layered semiconductor (WS2), a new type of ferroelectricity‐based synaptic transistor that differs from those relying on interface traps or floating gate configuration is reported. By virtue of a 6 nm thick ferroelectric hafnium zirconium oxide by atomic layer deposition and postannealing treatment, the device shows a channel resistance change ratio above 105 corresponding to opposite ferroelectric polarization direction. Furthermore, by applying electrical stimulus to the gate, it demonstrates good capability to mimic various synaptic behaviors including long‐term potentiation, long‐term depression, spike‐amplitude‐dependent plasticity, and spike‐rate‐dependent plasticity. Given the inherent compatibility of the ferroelectric gate stack with existing fabrication technology, and the reliability of ferroelectricity engineering, this work paves the way toward practical implementation of synaptic devices in neuromorphic circuits.

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“…Oxygen vacancies and oxygen interstitial atoms are considered to be the main origin of traps in HfO 2 -based materials. 22,23 When V g is swept toward a high positive value, electrons can tunnel through the 3 nm-thick Al 2 O 3 barrier into HfO 2 charge trapping layer by means of Fowler-Nordheim (FN) tunneling. 24,25 The resultant accumulation of electrons in HfO 2 trapping layer screens the control-gate electric field to reach the silicon channel, which results in a positive shift of the threshold voltage.…”

Section: Resultsmentioning

confidence: 99%

Fabrication and Characterization of p-Channel Charge Trapping Type FOI-FinFET Memory with MAHAS Structure

Hou¹,

Zhang²,

Yin³

et al. 2017

ECS J. Solid State Sci. Technol.

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A type of p-channel fin-on-insulator (FOI) FinFET charge trapping memory devices with HfO 2 charge trapping layer, Al 2 O 3 tunneling layer and blocking layers along with [TiN/W] metal gate (Metal/Al 2 O 3 /HfO 2 /Al 2 O 3 /Si, named as MAHAS in short) have been successfully fabricated. It is found that the new non-volatile memory, named in FOI-MAHAS memory shows better performance as compared with counterparts reported earlier owing to the adoption of p-type FOI channel and specific high-κ dielectrics. The static DC electrical characteristics of the fabricated memory devices including threshold voltage, subthreshold slope, gate breakdown voltage (BV g ), source-drain breakdown voltage (BV DS ) and memory characteristics such as program/erase (P/E) speed, memory window, endurance, and data retention at room temperature with different P/E approaches have been systematically investigated. A larger memory window, lower P/E voltages, improved P/E speed, as well as good data retention and endurance characteristics with band-to-band hot-electron (BBHE) programming are experimentally obtained. The developed p-channel FOI-MAHAS charge trapping memory is promising for the future nano-scaled NOR-type flash memory applications. It is well known that further scaling-down of the conventional bulk planar metal-oxide-semiconductor field-effect transistor (MOSFET) type NOR flash memory becomes very difficult because of the enhanced short-channel effect (SCE) induced by decreased gate control over channel region with the shrinkage of distance between source and drain. It is noteworthy that further scaling of planar NOR-type memory device faces the theoretical limit of source-drain breakdown voltage (BV DS ) which corresponds to the silicon (Si) and silicon dioxide (SiO 2 ) conduction band offset (3.2 eV). Thus, the scaled planar NOR-type flash memories with gate length (L g ) smaller than 100 nm are very difficult to fabricate.1-4 On the other hand, three-dimensional (3D) channel devices, such as fin field-effect transistors (FinFET) or fin-channel tri-gate (TG) device provide excellent SCE immunity thanks to the strong electrostatic controllability of the multiple gates. 5 Moreover, threshold voltage (V th ) variability in the FinFET or TG devices is much smaller than that in the conventional bulk planar MOSFETs because V th variation induced by the random dopant fluctuation (RDF) is negligible in FinFET or TG devices owing to the undoped fin-channels. Additionally, earlier study has shown that the electric field gets significantly enhanced in the curve part of the fin, thus the carrier injection rate from the channel gets substantially increased. As a result, the program and erase speeds of FinFET memory devices get obviously increased with respect to planer counterparts. [6][7][8][9] Recently a novel type of FinFET structure, named as fin-on-insulator (FOI) FinFET has been proposed.10,11 By adopting FOI structure, subsurface leakage paths in FinFETs are eliminated, the drain-induced barrier lowering (DIBL) is further reduced ...

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Charge-Trapping Phenomena in HfO₂-Based FeFET-Type Nonvolatile Memories

Cited by 243 publications

References 25 publications

A Thermodynamic Perspective of Negative-Capacitance Field-Effect Transistors

A Thermodynamic Perspective of Negative-Capacitance Field-Effect Transistors

A van der Waals Synaptic Transistor Based on Ferroelectric Hf_0.5Zr_0.5O₂ and 2D Tungsten Disulfide

Fabrication and Characterization of p-Channel Charge Trapping Type FOI-FinFET Memory with MAHAS Structure

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Charge-Trapping Phenomena in HfO2-Based FeFET-Type Nonvolatile Memories

Cited by 243 publications

References 25 publications

A Thermodynamic Perspective of Negative-Capacitance Field-Effect Transistors

A Thermodynamic Perspective of Negative-Capacitance Field-Effect Transistors

A van der Waals Synaptic Transistor Based on Ferroelectric Hf0.5Zr0.5O2 and 2D Tungsten Disulfide

Fabrication and Characterization of p-Channel Charge Trapping Type FOI-FinFET Memory with MAHAS Structure

Contact Info

Product

Resources

About

Charge-Trapping Phenomena in HfO₂-Based FeFET-Type Nonvolatile Memories

A van der Waals Synaptic Transistor Based on Ferroelectric Hf_0.5Zr_0.5O₂ and 2D Tungsten Disulfide