Charge Transport in Low-Temperature Processed Thin-Film Transistors Based on Indium Oxide/Zinc Oxide Heterostructures

Abstract

The influence of the composition within multilayered heterostructure oxide semiconductors has a critical impact on the performance of thin-film transistor (TFT) devices. The heterostructures, comprising alternating polycrystalline indium oxide and zinc oxide layers, are fabricated by a facile atomic layer deposition (ALD) process, enabling the tuning of its electrical properties by precisely controlling the thickness of the individual layers. This subsequently results in enhanced TFT performance for the optimized stacked architecture after mild thermal annealing at temperatures as low as 200 °C. Superior transistor characteristics, resulting in an average field-effect mobility (μ) of 9.3 cm V s ( W/ L = 500), an on/off ratio ( I/ I) of 5.3 × 10, and a subthreshold swing of 162 mV dec, combined with excellent long-term and bias stress stability are thus demonstrated. Moreover, the inherent semiconducting mechanism in such multilayered heterostructures can be conveniently tuned by controlling the thickness of the individual layers. Herein, devices comprising a higher InO/ZnO ratio, based on individual layer thicknesses, are predominantly governed by percolation conduction with temperature-independent charge carrier mobility. Careful adjustment of the individual oxide layer thicknesses in devices composed of stacked layers plays a vital role in the reduction of trap states, both interfacial and bulk, which consequently deteriorates the overall device performance. The findings enable an improved understanding of the correlation between TFT performance and the respective thin-film composition in ALD-based heterostructure oxides.

Corrugated Heterojunction Metal‐Oxide Thin‐Film Transistors with High Electron Mobility via Vertical Interface Manipulation

“…Although the surface roughness does not change during the deposition and patterning of the bottom ITZO layer, the wet etch and photolithography processes can produce defects or impurities which cause higher SS value. In addition, Krausmann et al reported the effect of channel layer thickness on the generation of bulk defects . In our results, regardless of the material, the TFT devices with thick active layer exhibits a higher SS value than those with thin active layer.…”

Atomic Layer Deposition of Ternary Indium/Tin/Aluminum Oxide Thin Films, Their Characterization and Transistor Performance under Illumination.

“…The measured growth rates of the individual metal oxides were found to be smaller than the ones calculated by the rule of mixture. This phenomenon is well documented and originates from a retarded adsorption of the precursors on the substrate [33] due to a changing surface chemistry during the deposition process [3] . To assess the homogeneity and the morphology of the deposited thin layers, high resolution transmission electron microscopy (HRTEM) was performed on a focused ion beam (FIB) prepared cross‐section of the deposited thin‐film (see Figure 2).…”

“…where V G , V T , and V P are the gate, threshold, and percolation voltages and K is a pre‐factor, the exponent γ is obtained, which provides information about the predominant transport mechanism [50] . Values for γ around 0.1 indicate a trap‐limited conduction (TLC), whereas values around 0.7 indicate a percolation conduction (PC) [3,50] . The dependency of the field‐effect mobility on the gate‐voltage for the discussed transistors is shown in Figure 7, while the respective values are summarized in Table 2.…”

Defect Self‐Compensation for High‐Mobility Bilayer InGaZnO/In2O3 Thin‐Film Transistor

“…However, disordered structural network and high density of intrinsic defects in the AOS materials largely affect electrical performances (e.g., electron mobility and stability) of the TFTs and limit their industrial applications in next‐generation electronic device platforms. To overcome these limitations, a notable strategy, i.e., stacked‐layer channel combining different individual oxide semiconducting materials, has been proposed in recent years and successfully implemented to enhance the device performances . Park and Lee reported a bilayer IZO/IGZO TFT with the field‐effect mobility (μ FE ) of 47.7 cm 2 V −1 s −1 and threshold voltage ( V TH ) of 1.57 V, where the mobility enhancement (i.e., ≈2.3 times higher than that of a single‐layer IGZO TFT) was induced by a high electron density of the IGZO layer with electrons injected from the IZO layer of the stacked structure .…”

“…Kim et al successfully fabricated the high‐performance oxide TFTs composed of the IZO (or InSnO) and IGZO active layers, showing μ FE of 51.3 cm 2 V −1 s −1 (104 cm 2 V −1 s −1 ), but the insight physics remained unexplored . The superior performance parameters of the stacked‐layer TFTs in refs were attributed to the formation of 2D electron gas (2DEG) at the heterointerface between the respective metal oxide film, where the 2DEG‐like system formed in the TFTs requires careful tuning of the quantized energy level in the semiconducting layers (e.g., In 2 O 3 /ZnO and In 2 O 3 /Al 2 O 3 ) as well as the suitable device architectures to enable a band‐like electron transport …”