Charge sharing problems in dynamic logic circuits: BiCMOS versus CMOS and a 1.5 V BiCMOS dynamic logic circuit free from charge sharing problems

Kuo, J.B.; Chiang, Cheng-Shing

doi:10.1109/81.477211

Cited by 5 publications

(5 citation statements)

References 10 publications

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“…Thus, the PMOS MP4 can be removed to enhance the evaluation speed. As a result, this circuit is similar to that proposed in [5]. Moreover, the charge-sharing problem can be avoided by adding an NMOS predischarge transistor in the pulldown section where the drain node and the gate node of this NMOS transistor are connected to the base node of Q2 and the gate node of MP1, respectively, as discussed in [5].…”

Section: New Tspc Bicmos Dynamic Logicmentioning

confidence: 89%

“…During the precharge phase, the internal-node precharge transistors MN to MN can be turned on to charge the internal nodes of the NMOS logic unit to -, where is the threshold voltage of NMOS transistors with the body effect. This nonfull-swing internal-node precharging technique [5], [9] is different from the conventional multiple precharging internal-node technique [22], which precharges the internal nodes to by PMOS transistors. Precharging to can enhance the evaluation speed while avoiding the chargesharing problem during the evaluation period.…”

Section: New Tspc Bicmos Dynamic Logicmentioning

confidence: 99%

“…Recently, many BiCMOS dynamic logic circuits have been proposed [2]- [5]. In the BiCMOS dynamic logic circuits proposed in [2]- [4], the N-P domino circuit structure with alternatively connected N-cell and P-cell [6], [7] is adopted.…”

mentioning

confidence: 99%

“…As the supply voltage is scaled down, the speed of some BiCMOS dynamic logic circuits [2], [3] is degraded significantly due to the loss in the output voltage swing [8]. In the BiCMOS domino circuit proposed in [5], only a precharge high P-cell is used to form the domino circuit for 1.5-V operation. However, if the logic function is complex, especially for dynamic OR gate implementation, the speed performance of the proposed logic is degraded due to the use of the PMOS logic unit.…”

mentioning

confidence: 99%

“…However, if the logic function is complex, especially for dynamic OR gate implementation, the speed performance of the proposed logic is degraded due to the use of the PMOS logic unit. Moreover, the pipelined system operation is not considered in [5].…”

mentioning

confidence: 99%

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A new true-single-phase-clocking BiCMOS dynamic pipelined logic family for high-speed, low-voltage pipelined system applications

Tseng

1999

IEEE J. Solid-State Circuits

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New true-single-phase-clocking (TSPC) BiCMOS/ BiNMOS/BiPMOS dynamic logic circuits and BiCMOS/BiNMOS dynamic latch logic circuits for high-speed dynamic pipelined system applications are proposed and analyzed. In the proposed circuits, the bootstrapping technique is utilized to achieve fast near-full-swing operation. The circuit performance of the proposed new dynamic logic circuits and dynamic latch logic circuits in both domino and pipelined applications are simulated by using HSPICE with 1-m BiCMOS technology. Simulation results have shown that the new dynamic logic circuits and dynamic latch logic circuits in both domino and pipelined applications have better speed performance than that of CMOS and other BiCMOS dynamic logic circuits as the supply voltage is scaled down to 2 V. The operating frequency and power dissipation/MHz of the pipelined system, which is constructed by the new clockhigh-evaluate-BiCMOS dynamic latch logic circuit and clock-lowevaluate-BiCMOS (BiNMOS) dynamic latch logic circuit, and the logic units with two stacked MOS transistors, are about 2.36 (2.2) times and 1.15 (1.1) times those of the CMOS TSPC dynamic logic under 1.5-pF output loading at 2 V, respectively. Moreover, the chip area of these two BiCMOS pipelined systems is about 1.9 times and 1.7 times as compared with that of the CMOS TSPC pipelined system. A two-input dynamic AND gate fabricated with 1-m BiCMOS technology verifies the speed advantage of the new BiNMOS dynamic logic circuit. Due to the excellent circuit performance in high-speed, low-voltage operation, the proposed new dynamic logic circuits and dynamic latch logic circuits are feasible for high-speed, low-voltage dynamic pipelined system applications. Index Terms-BiCMOS pipelined system, low-voltage BiCMOS dynamic logic circuits, true single-phase clocking (TSPC). I. INTRODUCTION B iCMOS technology has been widely applied to the design of memories and high-performance very-large-scale integrated circuit (VLSI) logic due to its advantageous features of high speed, high driving capability, and low power dissipation [1]. In the design of conventional BiCMOS static logic circuits, extra PMOS devices should be used with NMOS devices to realize logic functions. As a consequence, the chip area is large, especially in complex logic. Also, both power dissipation and speed performance are degraded.

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Section: New Tspc Bicmos Dynamic Logicmentioning

confidence: 89%

Section: New Tspc Bicmos Dynamic Logicmentioning

confidence: 99%