Charge recycling sense amplifier based logic: securing low power security ICs against DPA [differential power analysis]

Abstract

A Charge Recycling Sense Amplifer Based Logic is presented. This logic is derived from the Sense Amplifer Based Logic, which is a logic style with signal independent power consumption. It has been proven previously to protect security devices such a s Smart Cards against power attacks. Experimental results show that the use of advanced circuit techniques, which enable charge recycling and intermediate precharge voltages, saves 20% in power consumption and 63% in peak supply current and that the logic sfy/e preserves the energy nzasking behavior of rhe Sense Amplifer Based Logic.

Enhanced Current-Balanced Logic (ECBL): An Area Efficient Solution to Secure Smart Cards against Differential Power Attack

“…In this paper we suggest to use Enhanced Current Balanced Logic (ECBL) [2] to attain security directly at transistor level. Experiment results show that with a simpler circuit topology, ECBL reduces the current spikes up to 50% and 75% compared to those of SABL [4] and DyCML [5], respectively. The data hiding behavior of ECBL provides DPA resistance with approximately 25% to 30% area savings (in design of a XOR) compared to SABL and DyCML.…”

Experiments on two clock countermeasures against power analysis attacks

“…The goal of any DPA countermeasure is to make the power consumption of a cryptographic device independent from the internally processed data. Some countermeasures are based on suitable logical styles, (e.g., the SABL [2]), which aim at making the power consumption of the single logic gates uncorrelated with its logic state. Other countermeasures are based on special architectural arrangements, (e.g.…”

A Highly-Secured Arithmetic Hiding cum Look-Up Table (AHLUT) based S-Box for AES-128 Implementation

“…The WDDL and PCSL implement Pre-charge and Evaluation cycle with differential logic to make a constant power dissipation for different logic transition. In the AES-128 implementation, the WDDL occupies over 3.1× area, dissipate 3.7× dynamic power and 3.8× reduction in throughput compared with standard cell implementation [5]. For the PCSL implementation, the power dissipations tend to leak information during the pre-charge cycle [6] and hence vulnerable against CPA attack.…”

“…In other words, the dummy power dissipation is generated in such a way that overshadow the main power dissipation of the AES-128 algorithm, as expressed in Equation (4). In this context, the changes of POP and PDATA, are negligible respect to the total power traces which are used in the CPA attack as expressed in Equation (5). Eventually, the broken correlation, between power dissipation and processed data, is achieved due to the total power traces measured during the encryption is always referring to dummy operation, which is performing irrelevant operation and data with the operations in the AES-128 algorithm.…”

“…In the cell level, several techniques have been reported such as Sense Amplifier Based Logic (SABL) [5], Wave Dynamic Differential Logic (WDDL) [6], Three-phase Dual-rail Pre-charge Logic (TDPL) [7] and Pre-Charge Static Logic (PCSL) [8]. The concept of SABL is to balance internal charges by fully charging and discharging all internal node for different processed data (i.e.…”