Characterizing the Energy Consumption of Software Transactional Memory

Baldassin, Alexandro; Klein, Felipe; Araújo, Guido; Azevedo, Rodolfo; Centoducatte, Paulo Cesar

doi:10.1109/l-ca.2009.47

Cited by 10 publications

(15 citation statements)

References 13 publications

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“…In both [21,20] the authors assess the behaviour of different HTM implementations via simulation (the latter focusing on embedded systems). The approach was also taken by [2], where the power consumption of one STM was studied via simulation. More recently, [22] studied both power consumption and performance in a non-simulated environment.…”

Section: Related Workmentioning

confidence: 99%

Virtues and limitations of commodity hardware transactional memory

Diegues

Romano

Rodrigues

2014

Proceedings of the 23rd International Conference on Parallel Architectures and Compilation

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Over the last years Transactional Memory (TM) gained growing popularity as a simpler, attractive alternative to classic lock-based synchronization schemes. Recently, the TM landscape has been profoundly changed by the integration of Hardware TM (HTM) in Intel commodity processors, raising a number of questions on the future of TM.We seek answers to these questions by conducting the largest study on TM to date, comparing different locking techniques, hardware and software TMs, as well as different combinations of these mechanisms, from the dual perspective of performance and power consumption.Our study sheds a mix of light and shadows on currently available commodity HTM: on one hand, we identify workloads in which HTM clearly outperforms any alternative synchronization mechanism; on the other hand, we show that current HTM implementations suffer of restrictions that narrow the scope in which these can be more effective than state of the art software solutions. Thanks to the results of our study, we identify a number of compelling research problems in the areas of TM design, compilers and self-tuning.

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Section: Related Workmentioning

confidence: 99%

Virtues and limitations of commodity hardware transactional memory

Diegues

Romano

Rodrigues

2014

Proceedings of the 23rd International Conference on Parallel Architectures and Compilation

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“…A medição e análise do consumo de energia em sistemas transacionais foram inicialmente desenvolvidas em ambientes simulados, abordando sistemas com suporte em hardware para TM [18], [19]. Posteriormente sistemas em software também foram avaliados, usando a mesma infraestrutura de simulação [20], [21], [22]. Apesar de as análises iniciais serem válidas, ambientes simulados trabalham com algumas simplificações que podem afetar o resultado final.…”

Section: Trabalhos Relacionadosunclassified

Reavaliando a Eﬁciência Energética de Memória Transacional em Processadores Convencionais

Carvalho¹,

Baldassin²,

Azevedo³

2013

Anais Do XIV Simpósio Em Sistemas Computacionais De Alto Desempenho (SSCAD 2013)

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Memória Transacional (TM) é um mecanismo recente de sincronização que objetiva ao mesmo tempo facilitar o desenvolvimento de aplicações concorrentes e fornecer desempenho. A maioria dos trabalhos em TM focam avaliação de desempenho, negligenciando outras métricas como consumo de energia. Trabalhos anteriores analisaram a eﬁciência energética de implementações de TM através de ambientes simulados com modelo de execução simpliﬁcado. Este trabalho apresenta uma reavaliação do consumo de energia e desempenho de uma implementação moderna de memória transacional em processadores convencionais. Será descrito e discutido uma técnica de medição de energia baseada em Registradores Especíﬁcos de Modelo (MSRs), técnica essa utilizada para obter e analisar o consumo energético de aplicações transacionais do benchmark STAMP, bem como de suas respectivas implementações baseadas em travas. Também será discutido o comportamento do consumo de energia e desempenho devido à inﬂuência de diferentes gerenciados de frequência disponíveis em conﬁgurações típicas de sistemas Linux. Nossos resultados mostram que memória transacional em software de fato reduz o consumo de energia quando comparada a implementações baseadas em travas grossas em 7 das 8 aplicações estudadas em um processador Intel® Sandy Bridge™.

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“…The platform provides accurate power models for each component, characterized on a 0.13-μm technology by STMicroelectronics and validated on silicon. It has also been used by others to show the energy and performance impact of multiprocessor systems [21,9,2]. The precise configuration for the platform used in our experiments is given in Table 1.…”

Section: Simulation Platform and Applicationsmentioning

confidence: 99%

“…We are not aware of any other study on energy characterization of STM other than our previous works [2,17,18]. In this paper we cover a much broader spectrum of the STM design space, considering a new algorithm variation (encounter-time locking, lazy versioning) and two additional contention management policies (suicide and delay).…”

Section: Related Workmentioning

confidence: 99%

Energy-Performance Tradeoffs in Software Transactional Memory

Baldassin

Carvalho

Garcia³

et al. 2012

2012 IEEE 24th International Symposium on Computer Architecture and High Performance Computing

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Transactional memory (TM) is a new synchronization mechanism devised to simplify parallel programming, thereby helping programmers to unleash the power of current multicore processors. Although software implementations of TM (STM) have been extensively analyzed in terms of runtime performance, little attention has been paid to an equally important constraint faced by nearly all computer systems: energy consumption. In this work we conduct a comprehensive study of energy and runtime tradeoffs in software transactional memory systems. We characterize the behavior of three state-of-the-art lock-based STM algorithms, along with three different conflict resolution schemes. As a result of this characterization, we propose a DVFS-based technique that can be integrated into the resolution policies so as to improve the energy-delay product (EDP). Experimental results show that our DVFS-enhanced policies are indeed beneficial for applications with high contention levels. Improvements of up to 59% in EDP can be observed in this scenario, with an average EDP reduction of 16% across the STAMP workloads.

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Characterizing the Energy Consumption of Software Transactional Memory

Cited by 10 publications

References 13 publications

Virtues and limitations of commodity hardware transactional memory

Virtues and limitations of commodity hardware transactional memory

Reavaliando a Eﬁciência Energética de Memória Transacional em Processadores Convencionais

Energy-Performance Tradeoffs in Software Transactional Memory

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