Characterizing 3D Floating Gate NAND Flash

Xiong, Qin; Wu, Fei; Lu, Zhonghai; Zhu, Ying; Zhou, You; Chu, Yibing; Xie, Changsheng; Huang, Ping

doi:10.1145/3078505.3078550

Cited by 19 publications

(9 citation statements)

References 3 publications

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“…This leads to the increased cell failure rates with the number of P/E cycles. The error rate is -4 9 10  when the P/E cycles are 500 at the beginning of flash. When the P/E cycle is increased to 5000, the cell error rate is -3 6.8 10  , improving 7.6 times.…”

Section: Algorithm Verification and Analysismentioning

confidence: 99%

“…When programming the three pages of a one-word line, due to the coupling effect of parasitic capacitance [16], the program process has a disturb to the three pages of adjacent word lines that have been programmed. This makes the interfered three pages capture additional electrons, leading to threshold voltage drift [9] and easily resulting in bit errors, as shown in Figure 1. When the 3D-TLC NAND flash cell is affected by the program disturb, the window of threshold voltages transfers to the right and across the other windows, causing bit errors and thus affecting the reliability.…”

Section: Program Disturb Errormentioning

confidence: 99%

“…At present, the storage structure of NAND flash memory has changed from a traditional plane structure to a three-dimensional structure [4][5][6][7], which further improves the storage density. With the increase in storage density, data reliability [8] of flash memory has decreased [9]. To design effective algorithms for ensuring reliability, we must understand flash failure modes [10][11].…”

Section: Introductionmentioning

confidence: 99%

“…Some prior works [12,[16][17][18][19] mainly studied the error patterns of planar NAND flash memory, without systematically exploring the specific program disturb error patterns of 3D NAND flash memory. The previous work [9] only investigated error patterns of 3D-MLC NAND flash memory, without considering the error characteristics of 3D-TLC NAND flash memory [7].…”

Section: Introductionmentioning

confidence: 99%

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Program Disturb Research and Error Avoidance Algorithm Design of 3D-TLC NAND Flash Memory

Yang¹

2018

IJPE

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This paper focuses on finding, settling and reducing the program disturb error of 3D-TLC NAND flash memory. Experimental analysis of the FPGA test platform determines characteristics of the program disturb error. The program disturb error makes the state shift rate of storage cells lose balance. MSB, CSB and LSB pages have unbalanced bit error ratio and bit error rate distribution. The page program disturb bit error is unbalanced as the number of program/erase cycles changes. Based on the experimental results of the error rate imbalance, an error avoidance algorithm is designed, which can shift the data state that is subject to program disturb to one that is not vulnerable to program disturb. The test results show that the algorithm can reduce the error rate of program disturb by 20% to 90%. In this sense, the program disturb error phenomenon found and error avoidance algorithm designed in this paper are helpful for improving the reliability of 3D-TLC NAND flash memory.

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Section: Algorithm Verification and Analysismentioning

confidence: 99%

Section: Program Disturb Errormentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Program Disturb Research and Error Avoidance Algorithm Design of 3D-TLC NAND Flash Memory

Yang¹

2018

IJPE

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“…Although the acceleration method of retention errors based on this theory is widely applied in both academia and industry, it is generally accepted that this method cannot accurately represent the retention characteristics of planar flash memory at room temperature [10,15,20]. Currently, retention error characterization methods still apply the same model and parameters that are obtained on planar flash to high-density 3D NAND flash memories [33][34][35]. In this work, we will show that this model works even worse on 3D NAND flash memory, via studying long-retention errors of 3D flash chips with temperature considerations based on real data.…”

Section: Flash Retention Accelerationmentioning

confidence: 99%

How the common retention acceleration method of 3D NAND flash memory goes wrong?

Kuo

2021

Proceedings of the 13th ACM Workshop on Hot Topics in Storage and File Systems

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The reliability of solid-state drives (SSDs) has become increasingly important as SSDs are now widely applied in data centers. Retention error is a major source of impact on the reliability of SSDs. Even though the common practice in understanding the retention errors of an SSD is done by high-temperature baking processes, their characterization accuracy is not yet rigidly reviewed. In this paper, we first present how the common retention acceleration method goes wrong. Through a one-year study of 3D flash error behaviors, we found that the retention errors through baking with high temperatures have very different characteristics from the real long-retention errors. These differences come from the inherent structure and the materials of 3D NAND flash. Several findings regarding the retention errors characterized through baking are presented, followed by the analysis of the error behaviors. Finally, the retention errors of one year on 3D flash memory are provided with real data.

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RBER Aware Multi-Sensing for Improving Read Performance of 3D MLC NAND Flash Memory

Zhang

Chen

et al. 2018

IEEE Access

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Characterizing 3D Floating Gate NAND Flash

Cited by 19 publications

References 3 publications

Program Disturb Research and Error Avoidance Algorithm Design of 3D-TLC NAND Flash Memory

Program Disturb Research and Error Avoidance Algorithm Design of 3D-TLC NAND Flash Memory

How the common retention acceleration method of 3D NAND flash memory goes wrong?

RBER Aware Multi-Sensing for Improving Read Performance of 3D MLC NAND Flash Memory

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