Characterization, simulation and macro-modelling of vertical Hall devices

Randjelović, Z.; Popović, R.S.

doi:10.1016/s0026-2692(98)00038-x

Cited by 11 publications

(5 citation statements)

References 2 publications

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“…The minimum offset of the proposed folded vertical Hall device is 0.29 mV in type 5. This value is smaller than that of [20], 33.3 mV, and that of [21], 10 mV. Fig.…”

Section: Discussionmentioning

confidence: 59%

Interaction Between Magnetoresistor and Magnetotransistor in the Longitudinal and Folded Vertical Hall Devices

Sung

2004

IEEE Sensors J.

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This study investigates the one-dimensional longitudinal and folded vertical Hall devices, fabricated in a standard 0.35-m CMOS process. The smallest nonlinearity error 0.18%, the minimum offset 0.29 mV, and the maximum supply-current-related sensitivity RI = 3 837 V A T, are obtained with a 10-mA bias current excited by the supply voltage of 0.6 V. The main magnetic mechanism is that the filament current of the vertical magnetoresistor is directly injected into the base region of the bulk magnetotransistor (BMT) to increase the density of minority carriers and then enhance the magnetosensitivity. Furthermore, the induced Hall voltage of the longitudinal vertical Hall device is proportional to the bias current, but the folded vertical Hall device is inversely impacted. This advantage makes it possible to get a low-power folded vertical Hall device. The folded style not only reduces the nonlinearity error but also minimizes the offset. Unfortunately, the tradeoff is a fall in sensitivity. The BMT is applied to increase magnetic sensitivity and to compensate for this negative impact. Index Terms-Folded vertical Hall device, Hall effect, magnetoresistor (MR), magnetosensor, magnetotransistor (MT).

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“…The minimum offset of the proposed folded vertical Hall device is 0.29 mV in type 5. This value is smaller than that of [20], 33.3 mV, and that of [21], 10 mV. Fig.…”

Section: Discussionmentioning

confidence: 59%

Interaction Between Magnetoresistor and Magnetotransistor in the Longitudinal and Folded Vertical Hall Devices

Sung

2004

IEEE Sensors J.

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“…In this context, we recently developed a compact model of the electrical behavior of the VHD [5]. This model differs from other modeling approaches [6][7][8] (finite element modeling, lumped circuit ...) by its relative simplicity: it consists in 10 non-linear resistors and it is tuned through 14 parameters (7 of them being related to the geometry, 5 to the technology, and 2 are fitting parameters) [5]. Among all physical effects that alter the response of the sensor, the zero-tesla offset is one of the most critical [9].…”

Section: Introductionmentioning

confidence: 99%

Compact modeling of offset sources in vertical hall-effect devices

Madec

Osberger

Schell

et al. 2014

2014 IEEE 12th International New Circuits and Systems Conference (NEWCAS)

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Vertical Hall-effect devices are CMOS integrated sensors designed for the measurement of magnetic field in the plane of the chip. In such devices, systematic offset is a major issue which limits their performance. We recently developed a design-oriented compact model for such devices. In this paper, the model is improved and used to study the main features of the offset. There are two main phenomena that induce offset in the sensor: sensor imperfections (process deviation, mechanical stress …) which can be modeled by contact misalignments, and the modulation of the space charge region at the N-well/P-sub junction. Offset is modeled through 4 parameters which are extracted from offset measurement, and the model is validated with experimental results.

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“…Today, most of the existing VHD compact models are derived from HHD models, as for the Randjelovic's model [6]. This approach is interesting but remains nevertheless too rough to observe the phenomenon at the origin of distortions in the electrical response of the sensor (non-linearity, offset).…”

Section: Introductionmentioning

confidence: 99%

An improved compact model of the electrical behaviour of the 5-contact vertical hall-effect device

Madec

Schell

Kammerer

et al. 2013

2013 IEEE 11th International New Circuits and Systems Conference (NEWCAS)

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The goal of this work is the improvement of an existing design-oriented model of the 5-contact vertical Halleffect sensor integrated in CMOS technology. Such a model should facilitate the work of designers, permitting them to simulate the sensor, the biasing and processing electronics together with the same electrical simulator. In this paper, focus is put on two physical effects that alter the electrical behavior of the sensor: the carrier velocity saturation under high electric field, and the limitation of the current lines depth into a deep sensor. The model has been achieved with a subtle mix of theoretical considerations, numerical simulations performed with COMSOL Multiphysics  and experimental data. It has been compared with experimental data gathered from two devices, one fabricated in a low-voltage (LV) standard technology and another one in a high-voltage (HV) technology. Simulations obtained with the compact model fit the actual behavior of the LV-sensor with a root mean square error of 0.35%, and 0.8% for the HV-VHD.I.

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Characterization, simulation and macro-modelling of vertical Hall devices

Cited by 11 publications

References 2 publications

Interaction Between Magnetoresistor and Magnetotransistor in the Longitudinal and Folded Vertical Hall Devices

Interaction Between Magnetoresistor and Magnetotransistor in the Longitudinal and Folded Vertical Hall Devices

Compact modeling of offset sources in vertical hall-effect devices

An improved compact model of the electrical behaviour of the 5-contact vertical hall-effect device

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