2017 IEEE Optical Interconnects Conference (OI) 2017
DOI: 10.1109/oic.2017.7965506
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Characterization of systematic process variation in a silicon photonic platform

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Cited by 6 publications
(5 citation statements)
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“…A common solution for correcting PV-drifts is postfabrication calibration at the device level, which determines the fabric error through variation characterization during chip testing and then calibrate it carefully for every MR. No additional power is required after successful calibration. However, this technique is immature and less commercially practical [11], [12]. Firstly, it is difficult to do post-fabrication calibration for ONoCs where thousands and millions of MRs exist.…”
Section: Pv-tolerant Thermal Sensormentioning
confidence: 99%
“…A common solution for correcting PV-drifts is postfabrication calibration at the device level, which determines the fabric error through variation characterization during chip testing and then calibrate it carefully for every MR. No additional power is required after successful calibration. However, this technique is immature and less commercially practical [11], [12]. Firstly, it is difficult to do post-fabrication calibration for ONoCs where thousands and millions of MRs exist.…”
Section: Pv-tolerant Thermal Sensormentioning
confidence: 99%
“…We have therefore tested the system performance by adding a random deviation of ±7.5 nm to all the waveguides widths and their mutual distances. This deviation is compatible with fabrication errors in standard lithography [30,31]. When introducing this random deviation, the array symmetry with respect to the central waveguide is lost and we cannot therefore rely on Eq.…”
Section: Accepted Manuscriptmentioning
confidence: 87%
“…Si photonics, with its capacity for cost-effective fabrication of large-scale photonic ICs (PIC) can provide high-performance solutions for many important applications such as data-center interconnects, 1) sensors, 2,3) microwave photonics, 4,5) and newly emerging quantum 6,7) and neuromorphic computing. 8,9) For these applications, such process variations as those in silicon-on-insulator (SOI) thickness, waveguide width, and doping concentrations can greatly affect the performance and the yield of the resulting Si PICs, [10][11][12] and, consequently, their statistical distribution and its influence on the PIC performance must be carefully investigated. In the case of Si IC technology, the performance of the target IC can be very precisely predicted in the design stage by various corner simulations 13) and Monte Carlo analysis techniques 14) using the statistical data provided by the IC manufacturer.…”
Section: Introductionmentioning
confidence: 99%
“…The influence of waveguide geometry variation such as SOI thickness and waveguide linewidth was investigated. [10][11][12] Layout-aware behavioral simulations with the wafer-scale information on spatially correlated layout dependency were carried out. 15,16) However, there is a very limited number of publications 17,18) on the statistical investigation of active Si photonic devices such as modulators, although process variation can have significant influences on the Si active device characteristics and, consequently, the total performance of Si PICs.…”
Section: Introductionmentioning
confidence: 99%
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